Building Verification Infrastructure for Complex PCIe Verification
PCIe (Peripheral Component Interconnect Express) is a high-speed serial interconnect that is widely used in consumer and server applications. Over generations, PCIe has undergone diversified changes, spread across transaction, data link and physical layers. The latest PCIe 6.0 specification, too, has significant changes like the introduction of the flit concept, PAM4 signaling, L0p, shared flow control, and the fixed TLP format. The evolution of several generations has disrupted the existing design flow, thus making the verification process a critical and challenging aspect. Verifying all these new features and enhancements across several generations of PCIe while maintaining backward compatibility requires advanced system-level verification to ensure at a first-order that things did not break and then to verify the intricate new changes. There are several challenges in the verification, as mentioned further, which require corresponding great infrastructure to support it.
Related Semiconductor IP
- PCIe 6.0 PHY, TSMC N6 x2 1.2V, North/South (vertical) poly orientation
- PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, SS SF5A x1, North/South (vertical) poly orientation
Related Blogs
- Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application
- Industry's First Verification IP for PCIe 7.0
- Randomization considerations for PCIe Integrity and Data Encryption Verification Challenges
- PCIe Spread Spectrum Clocking (SSC) for Verification Engineers
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?