Building Verification Infrastructure for Complex PCIe Verification
PCIe (Peripheral Component Interconnect Express) is a high-speed serial interconnect that is widely used in consumer and server applications. Over generations, PCIe has undergone diversified changes, spread across transaction, data link and physical layers. The latest PCIe 6.0 specification, too, has significant changes like the introduction of the flit concept, PAM4 signaling, L0p, shared flow control, and the fixed TLP format. The evolution of several generations has disrupted the existing design flow, thus making the verification process a critical and challenging aspect. Verifying all these new features and enhancements across several generations of PCIe while maintaining backward compatibility requires advanced system-level verification to ensure at a first-order that things did not break and then to verify the intricate new changes. There are several challenges in the verification, as mentioned further, which require corresponding great infrastructure to support it.
To read the full article, click here
Related Semiconductor IP
- AXI Bridge with DMA for PCIe IP Core
- PCIe Gen 7 Verification IP
- PCIe Gen 6 Phy
- PCIe Gen 6 controller IP
- PCIe GEN6 PHY IP
Related Blogs
- Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application
- Randomization considerations for PCIe Integrity and Data Encryption Verification Challenges
- Accelerating PCIe Gen6 L0p Verification for AI & HPC Designs using Synopsys VIP
- Verification of PCIe's TDISP for Device Interface Security
Latest Blogs
- ReRAM in Automotive SoCs: When Every Nanosecond Counts
- AndeSentry – Andes’ Security Platform
- Formally verifying AVX2 rejection sampling for ML-KEM
- Integrating PQC into StrongSwan: ML-KEM integration for IPsec/IKEv2
- Breaking the Bandwidth Barrier: Enabling Celestial AI’s Photonic Fabric™ with Custom ESD IP on TSMC’s 5nm Platform