Breakthrough in area efficiency of on-chip ESD protection
November 13, 2023
ESD protection in the most advanced FinFET technology is challenging: The ESD design window (link) is extremely narrow in FinFET processes (link). Moreover, some of the conventional ESD solutions like the ggNMOS based protection are not effective anymore (link).
To protect sensitive FinFET circuits IC designers need to design the traditional ESD clamps and diodes a lot bigger. It is also required to reduce the distance between rail clamps and interface pads. It leads to an increase in ESD related area and increase in parasitic capacitance at the interfaces from scaling up the ESD (dual) diodes.
To read the full article, click here
Related Blogs
- Optimized on-chip ESD protection to enable high-speed Ethernet speed in cars
- ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
- The role of AI processor architecture in power consumption efficiency
- Selecting optimized ESD protection for CMOS image sensors
Latest Blogs
- Deploying StrongSwan on an Embedded FPGA Platform, IPsec/IKEv2 on Arty Z7 with PetaLinux and PQC
- The Rise of Physical AI: When Intelligence Enters the Real World
- Can Open-Source ISAs Catalyze Smart Manufacturing?
- The Future of AI is Modular: Why the SiFive-NVIDIA Milestone Matters
- Heterogeneous Multicore using Cadence IP