Breakthrough in area efficiency of on-chip ESD protection
November 13, 2023
ESD protection in the most advanced FinFET technology is challenging: The ESD design window (link) is extremely narrow in FinFET processes (link). Moreover, some of the conventional ESD solutions like the ggNMOS based protection are not effective anymore (link).
To protect sensitive FinFET circuits IC designers need to design the traditional ESD clamps and diodes a lot bigger. It is also required to reduce the distance between rail clamps and interface pads. It leads to an increase in ESD related area and increase in parasitic capacitance at the interfaces from scaling up the ESD (dual) diodes.
To read the full article, click here
Related Blogs
- Optimized on-chip ESD protection to enable high-speed Ethernet speed in cars
- ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
- Selecting optimized ESD protection for CMOS image sensors
- Designing Electrostatic Discharge (ESD) Protection for Monolithic SoCs and Multi-Die Systems
Latest Blogs
- The Perfect Solution for Local AI
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
- Analog Design and Layout Migration automation in the AI era
- UWB, Digital Keys, and the Quest for Greater Range
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design