Sofics IP
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10
IP
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10)
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1.8V general purpose I/O for 4nm FinFET
- Enable higher voltage operation, beyond the foundry IO levels
- Easily replace existing I/O cells
- Integrated scalable ESD protection
- Bias circuit can be shared with multiple I/Os
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3.3V general purpose I/O for 28nm CMOS
- Enable higher voltage operation, beyond the foundry IO levels
- Easily replace existing I/O cells
- Integrated scalable ESD protection
- Bias circuit can be shared with multiple I/Os
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High voltage tolerant I/O
- Scalable robustness
- Area efficient
- low capacitance option
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Small area rail clamp for FinFET
- Power clamp ESD solutions
- Rail clamp ESD protection
- 0.75V domain
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Analog I/O - low capacitance, low leakage
- Scalable robustness
- Area efficient
- low capacitance option
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on-chip ESD protection
- Analog I/Os
- ESD Power protection
- Ground pads
- ESD protection cells
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On-chip protection against IEC61000-4-2 events
- Analog Pads
- Power Pads
- Ground Pads
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I/O LIbrary
- Schmitt triggered input
- pull up/down control modes
- Slew rate controled output
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Die-2-die interfaces for chiplets
- Analog I/Os
- ESD Power protection
- Ground pads
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LIN PHY
- driver
- EMC/ESD protection
- Full LIN functionality