Behavioral Modeling of Clock/Data Recovery
May 1, 2014
Clock/Data recovery (CDR) is a tricky logic to implement correctly. To verify the clock/data recovery logic implemented in designs, the corresponding verification infrastructure needs to be modeled correctly.
This presentation aims to present the various issues faced for modeling CDR behaviorally along with their solutions.
The presentation starts off by explaining the need for CDR in the context of serial interfaces. It then explains how CDR would be done in an ideal scenario. Real issues like Jitter and PPM/Drift are then introduced along with techniques for handling these effects. Finally, a flow chart explains how an accurate behavioral model can be constructed.
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related Blogs
- TSMC Yields Recovery!
- In search of recovery
- TSMC UMC Lead Semiconductor Recovery - Record Year in 2010
- 2010 Semiconductor Recovery
Latest Blogs
- Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos
- Introducing the Akeana 1000 Series Processors
- How fast a GPU do you need for your user interface?
- PCIe 6.x and 112 Gbps Ethernet: Synopsys and TeraSignal Achieve Optical Interconnect Breakthroughs
- Powering the Future of RF: Falcomm and GlobalFoundries at IMS 2025