ARM's Cortex-A7 and A15: A Performance Versus Power Consumption Optimization Scheme
November 16, 2011
Last month's edition of InsideDSP included the article "NVIDIA and Qualcomm ARM Up Against Competitors," which discussed (among other things) NVIDIA's upcoming five-core Kal-El (i.e. Tegra 3) SoC. Tegra 3 combines four ARM Cortex-A9 cores built out of conventional 40 nm transistors and a fifth Cortex-A9 constructed from low-leakage (albeit switching speed-limited) circuits. The fifth core will operate stand-alone in low-performance usage scenarios (including, ironically, during high definition video playback sessions, thanks to the chip's dedicated-function hardware resources).
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related Blogs
- Altera's Next-Generation FPGAs: Advanced Process Lithographies Lead to Performance, Power Consumption Efficiencies
- ARM vs Intel...Performance? Power? OS support? Or ubiquity?
- Technical Comparison: USB Power Delivery r1.0 vs r2.0
- Next-Gen Cadence Tensilica Vision Processor Core Claims Big Performance, Energy Consumption Gains
Latest Blogs
- The Perfect Solution for Local AI
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
- Analog Design and Layout Migration automation in the AI era
- UWB, Digital Keys, and the Quest for Greater Range
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design