Cooking Up Better Performance for Arm-Based SoCs
With increasing complexity, ascertaining performance in Arm-based SoCs design has become challenging, as it involves system-wide protocols connecting multiple IP in collaboration to deliver the expected performance. Verification teams must do the performance verification at the system level to ensure data integrity and avoid any bandwidth throttling or cache coherency issues at a later stage. However, it is difficult for developers to evaluate this combination's performance running the anticipated mix of workloads. Integrating more functionality and multicores suits the customer's expectations and market demands, but it introduces tremendous challenges for SoC verification teams.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Blogs
- Altera's new ARM-based SoC FPGAs
- Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application
- Defacto SoC Compiler performance on AWS Graviton3
- Raspberry Pi Pico 2: Arm-based Development Board Delivers Higher, More Secure Performance for Commercial Applications
Latest Blogs
- A Low-Leakage Digital Foundation for SkyWater 90nm SoCs: Introducing Certus’ Standard Cell Library
- FPGAs vs. eFPGAs: Understanding the Key Differences
- UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
- RT-Europa: The Foundation for RISC-V Automotive Real-Time Computing
- Arm Flexible Access broadens its scope to help more companies build silicon faster