Defacto SoC Compiler performance on AWS Graviton3
Defacto SoC Compiler is a leading tool for System on Chip integration, allowing users to bring together various IP blocks such as CPU cores and interconnect fabrics according to relevant constraints and create the RTL needed to stich all these components together. SoC Compiler is used at Arm to accelerate the generation of top-level Verilog code while reducing the scope for errors.
As an important component within key IP design flows, ensuring that SoC Compiler is able to turn around results as quickly as possible is critical to maintaining the productivity of our engineers. With that in mind, we have been reviewing the performance of the tool on the latest Arm Architecture instances available within our compute environment.
Arm performed an analysis to validate the performance of Defacto’s SoC Compiler on a spread of machines across our AWS environment.
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