Reviewing the Latest Arm AMBA ACE5-Lite Protocol Specification Updates
In this blog we will review the newest features released as part of the Arm® AMBA® ACE5-Lite protocol, said to improve throughput and meet the low power demands of ever evolving complex multicore SoCs including cache coherency.
Overview
AMBA ACE5-Lite interfaces are used by I/O coherent managers that need to communicate to other fully coherent managers with caches in the system. Typically, AMBA ACE5-Lite interfaces are used alongside Arm AMBA 5 CHI RN-F interfaces as shown below.
To read the full article, click here
Related Semiconductor IP
- PUF-based Post-Quantum Cryptography (PQC) Solution
- OPEN Alliance TC14 10BASE-T1S Topology Discovery IP
- HBM4 PHY IP
- 10-bit SAR ADC - XFAB XT018
- eFuse Controller IP
Related Blogs
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets
- New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions
- New AMBA 5 ACE/AXI Specification: More About Atomic Transactions
- New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP