Reviewing the Latest Arm AMBA ACE5-Lite Protocol Specification Updates
December 12, 2022
In this blog we will review the newest features released as part of the Arm® AMBA® ACE5-Lite protocol, said to improve throughput and meet the low power demands of ever evolving complex multicore SoCs including cache coherency.
Overview
AMBA ACE5-Lite interfaces are used by I/O coherent managers that need to communicate to other fully coherent managers with caches in the system. Typically, AMBA ACE5-Lite interfaces are used alongside Arm AMBA 5 CHI RN-F interfaces as shown below.
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Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related Blogs
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets
- New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions
- New AMBA 5 ACE/AXI Specification: More About Atomic Transactions
- New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP