Untether 推出 2-PFLOPS AI 芯片并发布边缘路线图
By Sally Ward-Foxton, EETimes (August 23, 2022)
At Hot Chips this week, Untether unveiled its second-gen architecture for AI inference, the first chip using this architecture, as well as plans to expand to edge and endpoint accelerators.
Untether’s new architecture, internally codenamed Boqueria, addresses trends for very large neural networks, including transformer networks in natural language processing and beyond, endpoint applications that require power efficiency, and applications that require performance and power efficiency combined with prediction accuracy.
The first chip to use the Boqueria architecture, SpeedAI, is a data center inference accelerator capable of 2 PFLOPS of FP8 performance running at peak power consumption (66 W), or 30 TFLOPS/W based on a more usual 30-35 W power envelope. (Untether’s first generation chip, RunAI, could handle 500 TOPS of INT8.)
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related News
- 以色列初创公司NeuReality 将推出 7nm 数据中心 AI 芯片
- 受美国芯片禁令影响,台积电暂停为中国初创公司 Biren 制造 AI 芯片
- 采用灵活videantis 处理器平台的KI-FLEX 人工智能芯片成功流片
- 创意电子采用 Cadence 数字解决方案完成首款台积电 N3 制程芯片及首款 AI 优化的 N5 制程设计