Untether Unveils 2-PFLOPS AI Chip, Edge Roadmap
By Sally Ward-Foxton, EETimes (August 23, 2022)
At Hot Chips this week, Untether unveiled its second-gen architecture for AI inference, the first chip using this architecture, as well as plans to expand to edge and endpoint accelerators.
Untether’s new architecture, internally codenamed Boqueria, addresses trends for very large neural networks, including transformer networks in natural language processing and beyond, endpoint applications that require power efficiency, and applications that require performance and power efficiency combined with prediction accuracy.
The first chip to use the Boqueria architecture, SpeedAI, is a data center inference accelerator capable of 2 PFLOPS of FP8 performance running at peak power consumption (66 W), or 30 TFLOPS/W based on a more usual 30-35 W power envelope. (Untether’s first generation chip, RunAI, could handle 500 TOPS of INT8.)
To read the full article, click here
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related News
- ChipAgents Raises Oversubscribed $21M Series A to Redefine AI for Chip Design
- VSORA Launches Europe’s Most Powerful AI Inference Chip
- ADTechnology Collaborates with Euclyd to Develop Ultra-Efficient AI Chip for Datacenters
- Untether AI Joins UCIe Consortium to Drive Chiplet Technology and Energy-Centric AI Acceleration
Latest News
- Marvell Completes Acquisition of Celestial AI
- IntoPIX Showcases Next‑Gen IPMX & JPEG XS Innovations At ISE 2026
- NanoIC extends its PDK portfolio with first A14 logic and eDRAM memory PDK
- Qualitas Semiconductor Secures Strategic IP Licensing Agreement for MIPI Solutions
- Chinese RISC-V Chipmaker SpacemiT Launches K3 AI CPU, Highlighting the Rise of Open-Source Hardware in Intelligent Computing