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MACsec Engine IP

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Search (23)
Compare 23 MACsec Engine IP from 7 vendors (1 - 10)
  • 1G/2.5G/5G/10G/25G/50G MACsec
    • The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
    • It protects components in Ethernet networks especially high-speed Ethernet used in automotive, industrial, cloud, data center, and wireless infrastructure.
    • The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
    Block Diagram -- 1G/2.5G/5G/10G/25G/50G MACsec
  • AES-GCM MACsec (IEEE 802.1AE) and FC-SP Cores
    • Small size: Starting at less than 13K ASIC gates, 1.5 Gbps performance at less than 20K gates
    • Scalability to throughputs of 128 bits per clock with the capability of parallel cores at throughputs of 100 Gbps and above
    • Supports Galois Counter Mode Encryption and authentication (GCM-AES a.k.a. AES-GCM)
    • Includes AES-GCM encryption, AES-GCM decryption, key expansion and data interface
    Block Diagram -- AES-GCM MACsec (IEEE 802.1AE) and FC-SP Cores
  • DDR Encrypter
    • Protect the external memory
    • On-the-fly encryption
    • Optional authentication
    Block Diagram -- DDR Encrypter
  • Memory & Bus Protection IP Core
    • The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory.
    • It supports AHB/AXI slave/master interfaces, APB port for configuration purpose, and contains a cache. It is typically placed between the processor(s) and an external memory controller (DDRx).
    Block Diagram -- Memory & Bus Protection IP Core
  • Inline Decrypter IP Core
    • XIP (eXecution In Place) of encrypted code directly from Flash. (Optional xSPI controller)
    • Decryption based on AES fully compliant with NIST FIPS 197
    • AMBA Master/Slave interfaces
    Block Diagram -- Inline Decrypter IP Core
  • Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
    • One input word per clock without any backpressure
    • Design can switch stream, algorithm, mode, key and/or direction every clock cycle
    • GCM: throughput is solely determined by the data width, data alignment and clock frequency
    • XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
    Block Diagram -- Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
  • High-speed Inline Cipher Engine
    • The ICE-IP-338 data path can be scaled to widths that are multiples of 128 bit to allow a tradeoff between area and performance that best fits the target application.
    • Configuration options include or exclude support for CipherText Stealing (CTS), the GCM mode, and the SM4 algorithm and/or Datapath Integrity logic.
    • The cryptographic AES and SM4 primitives can be provided with or without side channel attack DPA countermeasures.
    Block Diagram -- High-speed Inline Cipher Engine
  • Inline memory encryption engine for ASIC SoCs
    • 128/512-bit (16-byte) encryption and decryption per clock cycle throughput
    • Bidirectional design including separate crypto channels for read and write requests, ensuring non-blocking Read
    • Read-modify-write supporting narrow burst access.
    • Zeroization and support for memory initialization
    • Latency: <28 clock cycles for unloaded READ
    Block Diagram -- Inline memory encryption engine for ASIC SoCs
  • Inline memory encryption engine, for FPGA
    • Performs encryption, decryption and/or authentication using AES Counter Mode (CTR) or Galois Counter Mode (GCM)
    • Supports AES key sizes 128 or 256
    • Internal key management with NIST-compliant key generation
    • Encrypt memory space into user-defined vaults, each with a unique key
    • Compatible with AMBA AXI4 interface
    • Supports hard or soft memory controllers in Xilinx FPGA and SoC devices
    • Supports multiprocessor systems
    Block Diagram -- Inline memory encryption engine, for FPGA
  • Inline cipher engine with AXI, for memory encryption
    • Throughput: 128 bit (16 Byte) wide encryption/decryption per cycle
    • Throughput: 1 tweak computation per 4 clock cycles
    • Bidirectional design including arbitration between read and write requests
    • Zero clock overhead for switching between encryption (write) and decryption (read)
    • 30-40 cycle data channel latency
    Block Diagram -- Inline cipher engine with AXI, for memory encryption
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