Secure-IC's Securyzr(TM) DDR Encrypter

Overview

The DDR encrypter IP Core module enables on-the-fly encryption and authentication to the external memory.

It supports AXI slave/master interfaces, APB port for configuration purpose. It is typically placed between the processor(s) and an external memory controller (DDRx). This IP Core improves tamper resistance by avoiding any modification, spoofing or analysis of external data.

Key Features

Protect the external memory
On-the-fly encryption
Optional authentication
Transparent for the processor
Scalable data bus width
AMBA Master/Slave interfaces
Multi-region management
Scalable throughput
ASIC and FPGA (incl. UltraScale+ & Versal)

Benefits

A high throughput DDR encrypter (100Gbps). The DDR encrypter IP Core module enables on-the-fly encryption and authentication to the external memory. It is highly configurable and may be optimized for various size, throughput, and latency trade-offs. The core is device independent and is highly portable.

Block Diagram

Applications

Defence
Data Center
Payment

Deliverables

Netlist or RTL
Scripts for synthesis & STA
Self-checking RTL test-bench
Documentation

Technical Specifications

Availability

Now

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