IP Catalog > Security IP > Interface Security IP > HDCP IP

HDCP IP

HDCP IP cores are intended to protect digitally copyrighted audio and video content as it travels across connections, such as HDMI® or DisplayPort™.

Explore our vast directory of HDCP IP Cores below.

All offers in HDCP IP
Filter
Filter

Login required.

Sign in

Search (22)
Compare 22 HDCP IP from 7 vendors (1 - 10)
  • 1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
    • The HDCP 2.3 Embedded Security Modules (ESMs) on DisplayPort are autonomous modules that provide designers with a complete and robust transmitter (TX) or receiver (RX) implementation of the HDCP 2.3 content-protection technology over DisplayPort wired connections, including USB Type-C/USB 3.1.
    • This solution helps designers shorten development cycles and fully meet the stringent compliance and robustness requirements of the DCP LLC licensing authority.
    Block Diagram -- 1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
  • HDCP Encryption-Decryption Engine
    • Real-time encryption/decryption
    • 8k compression available for select applications
    • Low gate count and low latency implementation
    • Supports HDCP 1.3 and 1.4
    Block Diagram -- HDCP Encryption-Decryption Engine
  • HDCP 2.x Transmitter IIP
    • Supports HDCP version 2.2 and 2.3 Specifications.
    • User keys can be loaded for Authentication.
    • Cipher text can be generated using Hardware/API for Authentication Protocol.
    • Supports Authentication Protocols.
    Block Diagram -- HDCP 2.x Transmitter IIP
  • HDCP 2.x Receiver IIP
    • Supports HDCP version 2.2 and 2.3 Specifications.
    • User keys can be loaded for Authentication.
    • Cipher text can be generated using Hardware/API for Authentication Protocol.
    • Supports Authentication Protocols.
    Block Diagram -- HDCP 2.x Receiver IIP
  • HDCP 1.x Transmitter IIP
    • Supports HDCP version 1.3 and 1.4 Specifications.
    • Supports full HDCP Transmitter functionality.
    • Fully synthesizable.
    • Static synchronous design.
    Block Diagram -- HDCP 1.x Transmitter IIP
  • HDCP 1.x Receiver IIP
    • Supports HDCP version 1.3 and 1.4 Specifications.
    • Supports full HDCP Receiver functionality.
    • Fully synthesizable.
    • Static synchronous design.
    Block Diagram -- HDCP 1.x Receiver IIP
  • HDCP Verification IP
    • Supports HDCP 1.4, HDCP 2.2 and HDCP 2.3 end to end protection.
    • Can handle HDCP encryption and decryption for 8 bit and 32 bit link symbol.
    • Capable of continuous link integrity check for all lanes and rates.
    • Supports aux transactions for authentication protocol.
    Block Diagram -- HDCP Verification IP
  • 1-port Receiver or Transmitter HDCP 2.3 on HDMI 2.1 ESM
    • Transmitter (TX), Receiver (RX) and Repeater (Rep) solutions
    • Silicon-proven. Widely deployed. Certified.
    • Compliant with the latest HDCP 2.3 content protection standard (backwards compatible with HDCP 2.2)
    • HDMI 2.0 RX/TX/Rep support
    Block Diagram -- 1-port Receiver or Transmitter HDCP 2.3 on HDMI 2.1 ESM
  • HDMI 2.0 RX Controller with HDCP
    • Support for key HDMI 2.0 features such as 4K x 2K resolution at 60 Hz frame rate, YCbCr 4:2:0 pixel encoding format, TMDS scrambling, High Dynamic Range (HDR), CEC 2.0 and 18.0 Gbps aggregate bandwidth
    • Compliant with HDMI 2.0 and HDCP 2.3, 1.2 specification
    • Optimized for low power and small area
    • Integrated audio return channel (ARC) block
    Block Diagram -- HDMI 2.0 RX Controller with HDCP
  • HDMI 2.0 TX Controller with HDCP
    • Support for key HDMI 2.0 features such as 4Kx2K resolution at 60 Hz frame rate, YCbCr 4:2:0 pixel encoding format, TMDS scrambling, High Dynamic Range (HDR), CEC 2.0, and 18.0 Gbps aggregate bandwidth
    • Compliant with HDMI 2.0 and HDCP 2.3, 1.2 specification
    • Optimized for low power and small area
    • Timing hardened blocks enable simplified placement and design closure
    Block Diagram -- HDMI 2.0 TX Controller with HDCP
×
Semiconductor IP