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IPsec and TLS Engine IP

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Compare 26 IPsec and TLS Engine IP from 9 vendors (1 - 10)
  • HDCP Verification IP
    • Supports HDCP 1.4, HDCP 2.2 and HDCP 2.3 end to end protection.
    • Can handle HDCP encryption and decryption for 8 bit and 32 bit link symbol.
    • Capable of continuous link integrity check for all lanes and rates.
    • Supports aux transactions for authentication protocol.
    Block Diagram -- HDCP Verification IP
  • 1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
    • The HDCP 2.3 Embedded Security Modules (ESMs) on DisplayPort are autonomous modules that provide designers with a complete and robust transmitter (TX) or receiver (RX) implementation of the HDCP 2.3 content-protection technology over DisplayPort wired connections, including USB Type-C/USB 3.1.
    • This solution helps designers shorten development cycles and fully meet the stringent compliance and robustness requirements of the DCP LLC licensing authority.
    Block Diagram -- 1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
  • HDCP Encryption-Decryption Engine
    • Real-time encryption/decryption
    • 8k compression available for select applications
    • Low gate count and low latency implementation
    • Supports HDCP 1.3 and 1.4
    Block Diagram -- HDCP Encryption-Decryption Engine
  • HDCP 2.x Transmitter IIP
    • Supports HDCP version 2.2 and 2.3 Specifications.
    • User keys can be loaded for Authentication.
    • Cipher text can be generated using Hardware/API for Authentication Protocol.
    • Supports Authentication Protocols.
    Block Diagram -- HDCP 2.x Transmitter IIP
  • HDCP 2.x Receiver IIP
    • Supports HDCP version 2.2 and 2.3 Specifications.
    • User keys can be loaded for Authentication.
    • Cipher text can be generated using Hardware/API for Authentication Protocol.
    • Supports Authentication Protocols.
    Block Diagram -- HDCP 2.x Receiver IIP
  • HDCP 1.x Transmitter IIP
    • Supports HDCP version 1.3 and 1.4 Specifications.
    • Supports full HDCP Transmitter functionality.
    • Fully synthesizable.
    • Static synchronous design.
    Block Diagram -- HDCP 1.x Transmitter IIP
  • HDCP 1.x Receiver IIP
    • Supports HDCP version 1.3 and 1.4 Specifications.
    • Supports full HDCP Receiver functionality.
    • Fully synthesizable.
    • Static synchronous design.
    Block Diagram -- HDCP 1.x Receiver IIP
  • Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
    • Protocol aware IPsec, SSL, TLS, DTLS, 3GPP, MACsec packet engine with classifier and in-line interface for multi-core server processors
    • 10-100 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, streaming and AMBA interface
    • Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP.
    Block Diagram -- Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
  • Multi-Protocol Engine, Look-Aside, 1 Gbps
    • Protocol-aware IPsec/TLS packet engine with Look-Aside interface for IoT.
    • Up to 1 Gbps, lowest gate count in the industry, just 100K gates (ex AMBA interface).
    • Supported by Driver Development Kit, QuickSec IPsec toolkit, Secure Boot Toolkit.
    Block Diagram -- Multi-Protocol Engine, Look-Aside, 1 Gbps
  • 1-port Receiver or Transmitter HDCP 2.3 on HDMI 2.1 ESM
    • Transmitter (TX), Receiver (RX) and Repeater (Rep) solutions
    • Silicon-proven. Widely deployed. Certified.
    • Compliant with the latest HDCP 2.3 content protection standard (backwards compatible with HDCP 2.2)
    • HDMI 2.0 RX/TX/Rep support
    Block Diagram -- 1-port Receiver or Transmitter HDCP 2.3 on HDMI 2.1 ESM
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