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VESA Display Stream Compression IP

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  • VESA Display Stream Compression (DSC) IP Core
    • Supports Versions 1.1, 1.2 and 1.2a
    • Supports RGB and YCbCr color spaces
    • 1-to-8 slice support
    Block Diagram -- VESA Display Stream Compression (DSC) IP Core
  • Display Stream Compression (DSC 1.2) Encoder
    • VESA DSC 1.2 Compliant
    • Capable of encoding up to 4K video at 30fps in FPGA and ASIC
    • 8K compression available for select applications
    Block Diagram -- Display Stream Compression (DSC 1.2) Encoder
  • Display Stream Compression (DSC 1.2) Decoder
    • VESA DSC 1.2 Compliant
    • Capable of decoding 4K video at 30fps in FPGA and ASIC
    • Decode 8K video at 30fps in ASIC applications
    Block Diagram -- Display Stream Compression (DSC 1.2) Decoder
  • Display Port 2.0 Verification IP
    • Full Display port 2.0 source device and sink device functionality.
    • Supports backward compatibility with previous versions upto DPv1.4a
    • Supports multi lanes upto 4 lanes.
    • Supports control symbols for framing.
    Block Diagram -- Display Port 2.0 Verification IP
  • Display Port Verification IP
    • Full Display port source device and sink device functionality.
    • Display port supports version 1.0,1.1,1.2,1.2a,1.3,1.4,1.4a and 2.0 specification.
    • Supports multi lanes upto 4 lanes.
    • Supports control symbols for framing(Both Default & Enhanced framing mode).
    Block Diagram -- Display Port Verification IP
  • Display Port Synthesizable Transactor
    • Supports full Display port source device and sink device functionality
    • Supports multi lanes upto 4 lanes
    • Supports control symbols for framing(Both Default & Enhanced framing mode)
    • Supports interlaced & non-interlaced video stream
    Block Diagram -- Display Port Synthesizable Transactor
  • VESA DSC Encoder IIP
    • Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
    • Full DSC Encoder functionality.
    • Supports below coding schemes,
    • Modified Median-Adaptive Prediction (MMAP)
    Block Diagram -- VESA DSC Encoder IIP
  • VESA DSC Decoder IIP
    • Compliant with VESA Display Stream Compression Version 1.1, 1.2 and 1.2a.
    • Full DSC Decoder functionality.
    • Supports below coding schemes,
    • Modified Median-Adaptive Prediction (MMAP)
    Block Diagram -- VESA DSC Decoder IIP
  • DISPLAY PORT TRANSMITTER IIP
    • Compliant with Display Port version 2.0 specification.
    • Supports full Display port Transmitter functionality
    • Supports multi lanes upto 4 lanes
    • Supports 10bit, 20bit, 40bit and 80bit parallel interfaces
    Block Diagram -- DISPLAY PORT TRANSMITTER IIP
  • VESA VDCM 1.2 Encoder
    • Compliant with the VESA DSC 1.2a and 1.1 specifications
    • Supports all DSC video formats: RGB, YCbCr, native 4:2:2/4:2:0, simple 4:2:2
    • Supports the latest interface standards: HDMI 2.1, MIPI DSI, DisplayPort
    • Configurable IP delivers low-power and small area
    Block Diagram -- VESA VDCM 1.2 Encoder
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