Vendor: SmartDV Technologies Category: Displayport

Display Port Synthesizable Transactor

Display port Synthesizable Transactor provides a smart way to verify the Display port version upto 2.0 component of a SOC or a AS…

Contact Provider Request Datasheet

Overview

Display port Synthesizable Transactor provides a smart way to verify the Display port version upto 2.0 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's Display port Synthesizable Transactor is fully compliant with standard Display port version upto 2.0 Specification and provides the following features.

Key features

  • Supports full Display port source device and sink device functionality
  • Supports multi lanes upto 4 lanes
  • Supports control symbols for framing(Both Default & Enhanced framing mode)
  • Supports interlaced & non-interlaced video stream
  • Supports nibble interleaving(ECC)
  • Supports main link, Aux link and Hot plug functionality
  • Supports fast link training
  • Supports full link training
  • Supports skip the link training
  • Supports spread Spectrum clocking (SSC)
  • Supports I2C over AUX CH and EDID
  • Supports symbol Stuffing and Transfer Unit
  • Supports 3D stereo
  • Supports ANSI8B10B encoding / decoding
  • Supports packing of all the video formats supported by the display port version upto 2.0
  • Supports packing of all secondary packet formats supported by the display port version upto2.0
  • Supports HPD based link training
  • Supports DPCD registers upto display port version 2.0 specification
  • Supports RGB, YCBCR444, YCBCR422, YCBCR420 and Y-Only RAW color format
  • Supports main stream attribute (MSA) packets
  • Supports following Secondary packets,
    • Audio timestamp
    • Audio stream
    • Extension
    • Audio copy management
    • ISRC
    • VSC
    • Camera SDP 8 to 15
    • Info frame formats
    • VSC extension VESA
    • VSC extension CEA
    • Picture Parameter Set(PPS)
    • Adaptive-Sync SDP
  • Supports Split SDP for both SST and MST mode
  • Supports packing of all audio formats supported by IEC 60958-1,IEC 60958-3,IEC 60958-4,IEC 61937-1,IEC 61937-3,CEA/CTA 861-F,861-G
  • Supports training pattern sequence (TPS2,TPS3,TPS4)
  • Supports interlane skew insertion in source mode
  • Supports deskew in sink device mode
  • Supports scrambler as in Display port specification
  • Scrambler can be enabled or disabled dynamically
  • Supports scrambler reset after every 512th symbol
  • Supports on the fly generation of data
  • Supports Multi Stream Transport (MST) operation
  • Supports Advanced Link Power Management to reduce wake latency
  • Supports GTC-based video timing synchronization
  • Supports Display Stream Compression (DSC) up to version 1.2a
  • Supports Forward Error Correction(FEC)
  • Supports 8bit and 16bit RAW interfaces
  • Supports 10bit,20bit and 40bit parallel interfaces
  • Supports high-bandwidth Digital Content Protection System version1.3 (HDCP v1.3)
  • Supports high-bandwidth Digital Content Protection System version2.2 (HDCP v2.2)
    • Supports for HDCP2.2 with full authentication
    • Supports for HDCP2.2 with bypass the authentication
  • Supports High-bandwidth Digital Content Protection System version2.3(HDCP v2.3)
  • Detects and reports the following errors
    • Invalid control character
    • Invalid data character
    • Invalid 10bit code
    • Sync errors
    • Scrambler errors
    • Single and multi-bit ECC errors
    • Invalid packing injection and detect
  • Supports LT-tunable Phy Repeater(LTTPR)
  • Supports Horizontal Blanking Expansion
  • Supports Jitter insertion for Main Link Clock and Aux Channel Clock
  • Supports Ultra-high Bit rates at 10, 13.5, and 20Gbps/lane link rates
  • Supports Panel Replay
  • Supports 128b/132b channel coding

Block Diagram

Display Port Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the Display port testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Display Port Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about Displayport IP core

VESA Adaptive-Sync V2 Operation in DisplayPort VIP

In a computer system, both the GPU as well as the monitor have a certain rate at which they render or update an image, respectively. The rate is nothing but the frequency at which the image is refreshed (updated in the image it shows/displays), usually expressed in hertz, and can vary based on the content displayed on the screen.

DisplayPort 2025: Navigating the Next Wave of Display Innovation

This article breaks down the latest DisplayPort trends, the key technological shifts driving the protocol forward, and the strategic challenges implementers need to navigate — especially as DisplayPort IP finds its way into increasingly safety-critical domains.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about DisplayPort IP cores

What is Display Port Synthesizable Transactor?

Display Port Synthesizable Transactor is a Displayport IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Displayport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Displayport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP