Display Stream Compression (DSC 1.2) Decoder

Overview

Key Features

• Capable of decoding up to 4K video at 30fps in FPGA and 8K video at 30fps in ASIC applications
• Low gate count and low latency implementation
• Three clock domains:
• Stream and APB clocks operate the applicable interfaces
• Independent decoder clock runs the core functions
• Fully compliant with the VESA DSC 1.2 standard
• Uses synchronous design techniques and a technology abstraction layer for internal SRAM buffers
• Allows for migration from FPGA or FPGA prototype to ASIC with no functional changes to the core.
• Completely pipelined; can be stalled as necessary to properly manage input and output rates

Block Diagram

Technical Specifications