Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resolution video technologies. Bitec offer a highly optimized implementation of the DSC 1.2a as a stand-alone component and/or an integrated component to the Bitec DisplayPort 1.4 and HDMI 2.1 IP Cores.
Display Stream Compression offers inter-operable, visually lossless, real-time video compression to satisfy the emerging high bandwidth and high resolution video technologies. Bitec offers a highly optimized implementation of the DSC 1.2a as a stand-alone component and/or integrated component to the Bitec DisplayPort 1.4 and HDMI 2.1 IP Cores.
The DSC encoder or decoder has a rich set of parameterizations to enable an optimal customer implementation. User parameterized number of slices enables targeting of different transport protocols such as MIPI or DisplayPort.
VESA Display Stream Compression (DSC) IP Core
Overview
Key Features
- Supports Versions 1.1, 1.2 and 1.2a
- Supports RGB and YCbCr color spaces
- 1-to-8 slice support
- Optional support for Block Prediction
- Parameterized video geometry
- 4:4:4, 4:2:2 and 4:2:0 color spaces
Block Diagram
Deliverables
- The Bitec DSC IP Core is delivered with testbenches, documentation and example implementations for DisplayPort and HDMI 2.1.
Technical Specifications
Related IPs
- Display Stream Compression (DSC 1.2) Decoder
- Display Stream Compression (DSC 1.2) Encoder
- VESA DSC 1.1 Encoder IP Core for Automotive Displays (ASIL-B Ready ISO 26262 Certified)
- MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays
- JPEG XS compression IP core for HD - Max fps: 60 - Color sampling: 4:2:2 / 4:0:0
- VESA DSC Encoder