IP Catalog > Interface IP > Video Interface IP > DisplayPort IP > Display Port Verification IP

Display Port Verification IP

Overview

Display port is the serial communication protocol developed by Video Electronics Standards Association to support the video,audio and other data between a source device and sink device. Display port VIP can be used to verify transmitter or Receiver device following the Display port basic protocol as defined in Display port.

Display Port Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Display Port Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Full Display port source device and sink device functionality.
  • Display port supports version 1.0,1.1,1.2,1.2a,1.3,1.4,1.4a and 2.0 specification.
  • Supports multi lanes upto 4 lanes.
  • Supports control symbols for framing(Both Default & Enhanced framing mode).
  • Supports serial & parallel bit ordering.
  • Supports Interlaced & non-interlaced video stream.
  • Supports Nibble interleaving(ECC).
  • Supports main link, Aux link and Hot plug functionality.
  • Supports Fast link training.
  • Supports Full link training.
  • Supports skip the link training.
  • Supports Spread Spectrum clocking (SSC).
  • Supports I2C over AUX CH.
  • Supports to access EDID, Display ID via I2C over AUX.
  • Supports Symbol Stuffing and Transfer Unit.
  • Supports 3D stereo.
  • Supports ANSI8B10B encoding / decoding.
  • Supports Serialization and de-serialization.
  • Supports packing of all the video formats supported by the display port version 1.0,1.1,1.2/1.2a/1.3/1.4/1.4a/2.0.
  • Supports packing of all secondary(audio) formats supported by the display port version 1.0,1.1,1.2/1.2a/1.3/1.4/1.4a/2.0.
  • Supports HPD based link training.
  • Supports DPCD registers upto DPv2.0 specification.
  • Supports RGB, YCBCR444, YCBCR422, YCBCR420 and Y-only RAW color format.
  • Supports Main Stream Attribute (MSA) packets.
  • Supports following Secondary packets,
    • Audio timestamp
    • Audio stream
    • Extension
    • Audio copy management
    • ISRC
    • VSC
    • Camera SDP 8 to 15
    • Info frame formats
    • VSC extension VESA
    • VSC extension CEA/CTA
    • Picture Parameter Set (PPS).
    • Adaptive-Sync SDP
  • Supports Split SDP for both SST and MST mode.
  • Supports packing of all audio formats supported by IEC 60958-1, IEC 60958-3, IEC 60958-4, IEC 61937-1, IEC 61937-3, CEA 861-F/CTA-861, CEA-861.2/CTA-861.2, CEA-861.3/CTA-861.3,CEA 861-G
  • Supports training pattern sequence(TPS2, TPS3 and TPS4).
  • Supports interlane skew insertion in source mode.
  • Supports deskew in sink device mode.
  • Supports scrambler as in Display port specification.
  • Scrambler can enabled or disabled dynamically.
  • Supports scrambler reset after every 512th symbols.
  • Supports on the fly generation of data.
  • Supports Multi Stream Transport (MST) operation.
  • Supports Advanced Link Power Management to reduce wake latency
  • Supports GTC-based video timing synchronization
  • Supports Display Stream Compression (DSC) up to version1.2a.
  • Supports Cyclic Redundancy Checks for Display Stream Compression
  • Supports Forward Error Correction (FEC).
  • Supports 8bit and 16bit RAW interfaces.
  • Supports 10bit, 20bit and 40bit parallel interfaces.
  • Supports High-bandwidth Digital Content Protection System version1.3 (HDCP v1.3)
  • Supports High-bandwidth Digital Content Protection System version2.2 (HDCP v2.2)
    • Supports for HDCP2.2 with full authentication.
    • Supports for HDCP2.2 with bypass the authentication.
  • Supports High-bandwidth Digital Content Protection System version2.3 (HDCP v2.3)
  • Detects and reports the following errors,
    • Invalid control character
    • Invalid data character
    • Invalid 10bit code
    • Sync errors
    • Scrambler errors
    • Single and multi bit ECC errors
    • Invalid packing injection and detection
  • Supports LT-tunable Phy Repeater(LTTPR).
  • Supports Horizontal Blanking Expansion
  • Supports jitter insertion for Main link Clock and Aux Channel Clock
  • Supports RBR, HBR, HBR2, HBR3
  • Supports Ultra-high Bit rates at 10, 13.5, and 20Gbps/lane link rates
  • Supports Panel Replay
  • Supports 128b/132b channel coding
  • Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Status counters for various events on bus.
  • Callbacks in node transmitter, receiver and monitor for user processing of data.
  • Display port Verification IP comes with complete testsuite to test every feature of Display port version 1.0,1.1,1.2/1.2a/1.3/1.4/1.4a/2.0 specifications.
  • Functional coverage for complete Display port features.

Benefits

  • Faster testbench development and more complete verification of Display port designs.
  • Easy to use command interface simplifies testbench control and configuration of receiver and transmitter.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

Display Port Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the Display port testcases.
  • Examples showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Technical Specifications

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