32-Bit Microprocessor IP
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32-Bit Microprocessor IP
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55
32-Bit Microprocessor IP
from 23 vendors
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10)
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Tensilica ConnX 110/120
- Certified ISO 26262:2018 ASIL-compliant
- VLIW parallelism issuing multiple concurrent operations per cycle
- 128-bit or 256-bit SIMD
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Tensilica ConnX B10/B20
- Single-instruction, multiple-data (SIMD) vector processing
- Up to 5-issue very long instruction word (VLIW) for parallel load/store, MAC, and ALU ops
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Tensilica Fusion F1 DSP
- Specialized design to take advantage of sparsity in weights and activations for compute and bandwidth reduction
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32-bit High Performance RV32GC Single/Multicore RISC System-on-Chip
- High Performance 32-bit RV32GC CPU
- Proprietary 6-stage pipeline
- Single or multicore implementation
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32-bit High Performance RV32GC Single/Multicore RISC Processor
- High Performance 32-bit RV32GC CPU
- Proprietary 6-stage pipeline
- Single or multicore implementation
- Up to 1.38 DMIPS/MHz/Core
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Compact High-Speed 32-bit CPU Core
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- Andes extensions, architected for performance and functionality enhancements
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
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Superscalar 32-bit Processor
- Dual-issue pipeline
- Caches for fast code and data accesses
- Local Memories for deterministic code and data accesses
- Built-in IEEE754-compliant FPU coprocessor (N15F)
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Full-featured Real-time Application Processor
- Caches for fast code and data accesses
- Local Memories for deterministic code and data accesses
- IEEE754-compliant FPU coprocessor
- Memory Protection Unit (MPU) for secure RTOS
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DSP Extention Superscalar Processor
- Dual-issue pipeline
- > 130 DSP extension instructions
- Caches for fast code and data accesses
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32-bit High Performance Single/Multicore RISC Processor with code compression
- High Performance 32-bit RISC CPU
- Proprietary 6-stage pipeline
- 16-bit code compression
- Single or multicore implementation
