Multiprocessor, 4-Way Simultaneous Multithreading

Key Features

• Efficient Throughput
• Efficient data-centric processing with simultaneous multi-threading (SMT), low latency and deterministic data access
• 3-Wide, 9-stage, in-order pipeline with 1-, 2-, 4-way SMT
• RISC-V Compliant ISA
• RV64GHZ + Bitmanip Zba and Zbb, + CMO Extension
• MIPS User-Defined Instructions (UDI)—Cache and TLB management, Performance enhancements and DVM (Distributed Virtual Memory) support
• Optional 64KB Data ScratchPad RAM (DSPRAM) for real-time, low-latency applications
• Coherence Manager
• Support for up to 8 coherent initiators comprising of either MIPS RISC-V Processors or 3rd party accelerators
• Cluster Level-2 Cache L2$ up to 8MB
• HW pre-fetch, widened busses, reduced latency
• System interface:
• ACE or AXI: 256-bit system bus
• Optional: Non-coherent periphery bus (up to 4 ports)

Benefits

• Triple-issue In-order
• Up to 4-way Simultaneous Multi-threading
• Up to 8 Cores per Cluster
• Automotive Capable ASIL-B

Block Diagram

Technical Specifications