IP Catalog > Processor IP > General Purpose Processor IP > 32-Bit Microprocessor IP > 32-Bit Automotive Processor - 3-Stage Pipeline, Single/Dual-issue

32-Bit Automotive Processor - 3-Stage Pipeline, Single/Dual-issue

Overview

NA300 series processor is a ISO26262 ASIL-B/D Certified RISC-V CPU IP,Nuclei self-developed STL supports multiple ASIL-B automotive use cases.

NA300D Series

  • Systematic Capability:ASIL D
  • Hardware Safety Integrity: ASIL D in DCLS mode

NA300B Series

  • Systematic Capability:ASIL D
  • Hardware Safety Integrity: ASIL B
  • Nuclei self developed Softwate Test Library for ASIL B application
  • Fault Injection simulation FMEDA report for configurable design
  • ASIL B support fot both split mode and singlecore mode
  • Safety enhanced hardware for trade-off between diagnostic coverage and hardware cost

Key Features

  • RV32IMACFDBPC/Zcxlcz ISA supported
  • Dual-issue, in-order 3 stage Harvard Pipeline
  • Support fast interrupts tail-chaining mechanism , vectored interrupt processing mode for extremely fast interrupt response, and interrupt preemptions based on interrupt levels.
  • Configurable ILM/DLM
  • Configurable Instruction-Cache
  • Configurable Data-Cache
  • Support single/double float and SIMD DSP.
  • Support TEE
  • Configurable Issue
  • Full Standard Debug Function with JTAG port.
  • Full Standard RISC-V Toolchain, and Linux/Windows IDE supported

Benefits

  • Great Power Efficiency
  • RV32IMACFD BPC/Zcxlcz
  • 3-stage Pipeline Dual-issue
  • Machine, User, Supervisor-Mode
  • Security (PMP)
  • AHB-Lite System Bus
  • RISC-V Standard Debug
  • JTAG & cJTAG
  • Low Latency Interrupt
  • Full Dev Kit & SDK

Block Diagram

32-Bit Automotive Processor - 3-Stage Pipeline, Single/Dual-issue Block Diagram

Technical Specifications

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32-Bit Automotive Processor - 3-Stage Pipeline, Single/Dual-issue
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