IP Catalog > Processor IP > General Purpose Processor IP > 32-Bit Microprocessor IP > 32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue

32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue

Overview

With extreme low area, N100 is a 32b RISC-V processor designed specifically for low power application. N100 aims for cost sensitive application including IoT, MCU, sensor.

100 Series Performance and Configurability

Nuclei CPU IP N100
Pipeline Stages 2
Issue-Width Single-Issue
Hardware Multiplier Configurable
Hardware Divider Configurable
RISC-V ZC Extension Configurable

Key Features

  • Support RV32I/EMC/Zc ISA.
  • 2-stage pipeline, extremely optimized micro-archtecture for low power and area.
  • Configurable single cycle and multiple cycle Multiplier
  • 32 Bits AHB-Lite system bus
  • Configurable Divider
  • Machine mode
  • Configurable IRQC
  • Full Standard Debug Function with JTAG/cJTAG port.
  • Full Standard RISC-V Toolchain, and Linux/Windows IDE supported

Benefits

  • Ultra-LowPower
  • RV32I/EMC/Zc
  • 2 Stage Pipeline
  • Machine-Mode
  • AHB-Lite
  • Multiplier-divider
  • RISC-V Standard Debug
  • JTAG & cJTAG
  • Low Latency Interrupt
  • Full Development Toolkit

Block Diagram

32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue Block Diagram

Technical Specifications

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32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue
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