General Purpose DSP IP

Compare 18 General Purpose DSP IP from 13 vendors (1 - 10)

16 bit DSP fixed point coprocessor
- The APS DSP has been designed from the ground up as a companion to the APS family of processors, ensuring simple integration into your embedded system.
- The additional instructions are fully integrated with the assembler and simple macros make using the DSP from C or C++ very simple.
18-Bit Pipeline DSP Slice IP
- Timing resolution: 80ps
- Operating frequency range: 160MHz – 700 MHz
- Lock time: 11 cycles
- Generates user configurable precise phase shifts from 00 to 3600 with a resolution of 10
Multipurpose Hybrid DSP and Controller Architecture Family
- Parallel processing SIMD Instruction Set Architecture
- 5-way VLIW micro-architecture
- Single or dual scalar compute engines
Complex DSP Engine Core
- Consists of Conjugation unit, Complex Multiplier, Pre-adder and two Complex Accumulators (X and Y).
- Parameterizable input widths
- Parameterizable accumulator widths
- Full precision multiplier output available
Ultra low power C-programmable Baseband Signal Processor core
- Ultra low power consumption
- Highly optimizing C-compiler software toolkit
- Minimal core size (65k gates), excluding debug interface (6k gates)
- Small memory footprint
Ultra low power C-programmable DSP core
- Ultra low power consumption
- Highly optimizing C-compiler software toolkit
- Minimal core size (43k gates), excluding debug interface (6k gates)
- Small memory footprint
16-bit Fixed-Point DSP
- 16 bit fixed point customizable DSP
- Single cycle 16 bit signed/unsigned multiplier
- 1 or more 40bit accumulator(s)
- 64k X data, Y data and program memory range
Tensilica FloatingPoint KQ7/KQ8 DSPs
- VLIW parallelism issuing multiple concurrent operations per cycle
- 512-bit and 1024-bit SIMD
- IEEE 754 vector floating-point (HP, SP, DP)
- Performance-optimized fused multiply-add (FMA)
Tensilica FloatingPoint KP1/KP6 DSPs
- VLIW parallelism issuing multiple concurrent operations per cycle
- Xtensa LX Secure Mode
- 128-bit and 512-bit SIMD
- IEEE 754 vector floating-point
High performance DSP core with VLIW/SIMD/decoupled architectures
- 32/64-bit RISC Core
- 3 scalar instructions per clock cycle (ALU operation, address modification and memory read/write operation)
- 64-bit Vector Coprocessor (fixed point):
- Programmable data length from 2 to 64 bits packed to 64 bit data words