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General Purpose DSP IP

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Search (16)
Compare 16 General Purpose DSP IP from 11 vendors (1 - 10)
  • Ultra-low-power Processor based on RISC-V Architecture
    • The icyflex-V processor is a new ultra-low-power core based on the RISC-V 32-bit ISA, compatible with off-the-shelf open-source and/or proprietary programming tools.
    • This new development represents a cost effective yet performing alternative to proprietary cores for next-generation ultra-low-power system-on-chip developments.
    • The core was optimized for performance, code density and power consumption and delivers up to 3.2 CoreMark/MHz while consuming as low as 14 uA/MHz in TSMC 55 nm low-power process.
    Block Diagram -- Ultra-low-power Processor based on RISC-V Architecture
  • 16 bit DSP fixed point coprocessor
    • The APS DSP has been designed from the ground up as a companion to the APS family of processors, ensuring simple integration into your embedded system.
    • The additional instructions are fully integrated with the assembler and simple macros make using the DSP from C or C++ very simple.
    Block Diagram -- 16 bit DSP fixed point coprocessor
  • Complex DSP Engine Core
    • Consists of Conjugation unit, Complex Multiplier, Pre-adder and two Complex Accumulators (X and Y).
    • Parameterizable input widths
    • Parameterizable accumulator widths
    • Full precision multiplier output available
    Block Diagram -- Complex DSP Engine Core
  • 18-Bit Pipeline DSP Slice IP
    • Timing resolution: 80ps
    • Operating frequency range: 160MHz – 700 MHz
    • Lock time: 11 cycles
    • Generates user configurable precise phase shifts from 00 to 3600 with a resolution of 10
    Block Diagram -- 18-Bit Pipeline DSP Slice IP
  • Ultra low power C-programmable Baseband Signal Processor core
    • Ultra low power consumption
    • Highly optimizing C-compiler software toolkit
    • Minimal core size (65k gates), excluding debug interface (6k gates)
    • Small memory footprint
    Block Diagram -- Ultra low power C-programmable Baseband Signal Processor core
  • Ultra low power C-programmable DSP core
    • Ultra low power consumption
    • Highly optimizing C-compiler software toolkit
    • Minimal core size (43k gates), excluding debug interface (6k gates)
    • Small memory footprint
    Block Diagram -- Ultra low power C-programmable DSP core
  • 16-bit Fixed-Point DSP
    • 16 bit fixed point customizable DSP
    • Single cycle 16 bit signed/unsigned multiplier
    • 1 or more 40bit accumulator(s)
    • 64k X data, Y data and program memory range
    Block Diagram -- 16-bit Fixed-Point DSP
  • Tensilica FloatingPoint KQ7/KQ8 DSPs
    • VLIW parallelism issuing multiple concurrent operations per cycle
    • 512-bit and 1024-bit SIMD
    • IEEE 754 vector floating-point (HP, SP, DP)
    • Performance-optimized fused multiply-add (FMA)
  • Tensilica FloatingPoint KP1/KP6 DSPs
    • VLIW parallelism issuing multiple concurrent operations per cycle
    • Xtensa LX Secure Mode
    • 128-bit and 512-bit SIMD
    • IEEE 754 vector floating-point
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Semiconductor IP