Ultra low power C-programmable DSP core

Overview

NXP conducts a successful licensing program for this embedded DSP core for ultra low power applications. Based on many years of experience in the design of ultra low power electronics, the core was developed for portable audio applications, including audio encoding and decoding, sound enhancement algorithms, and noise suppression. Products powered by CoolFlux DSP include hearing devices, mobile phones, portable audio players and portable media players.

NXP distributes the CoolFlux DSP core through its corporate Innovation & Technology (I&T) division with license support of NXP's Intellectual Property & Licensing Department (IP&L).

Key Features

Ultra low power consumption
- 25 µW/MHz @ 0.9 V (65 nm CMOS)
- 45 µW/MHz @ 1.2 V (65 nm CMOS)
- 34 µW/MHz @ 0.9 V (90 nm CMOS)
- 60 µW/MHz @ 1.2 V (90 nm CMOS)
- 45 µW/MHz @ 0.9 V (130 nm CMOS)
- 80 µW/MHz @ 1.2 V (130 nm CMOS)
- 60 µW/MHz @ 0.9 V (180 nm CMOS)
- 240 µW/MHz @ 1.8 V in (180 nm CMOS)
Highly optimizing C-compiler software toolkit
Minimal core size (43k gates), excluding debug interface (6k gates)
Small memory footprint
Performance (Worst Case Commercial Conditions, standard VT)
- 160 MHz @ 1.8 V 180 nm CMOS
- 200 MHz @ 1.2 V 130 nm CMOS
- 245 MHz @ 1.2 V 90 nm CMOS
- 300 MHz @ 1.2 V 65 nm CMOS (>2300 MOPS peak)
Extensive software library for audio decoding and advanced sound enhancement algorithms

Block Diagram

Deliverables

The CoolFlux DSP is available on FPGA board for testing and analyzing. Or you can evaluate the CoolFlux using the software toolkit.

Technical Specifications

Availability

now

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