16-bit Fixed-Point DSP

Overview

Key Features

• 16 bit fixed point customizable DSP
• Single cycle 16 bit signed/unsigned multiplier
• 1 or more 40bit accumulator(s)
• 64k X data, Y data and program memory range
• Supports pseudo floating point arithmetic
• 32bit barrel shifter
• Low latency interrupts and sleep mode
• Powerful built-in hardware debugger
• C-compiler, assembler, linker and debugger
• Straight forward system embedding
• Fully synchronous, technology independent
• VHDL model for synthesis and simulation
• Open and customizable architecture, instruction plug-in: iniDSP is fast where you need the power!
• Lowest Power Consumption: < 100uA / MIPS
• 80MIPS on 0.18 micron ASIC proven
• Evaluation platform available (FPGA and ASIC)

Benefits

• Low voltage and low power solutions, optimized for your specific algorithms.
• Straight forward implementation techniques sqeeze your schedule down.
• Application proven bus interface, synchronous clocking structure and a comprehensive, transparent architecture help to reduce evaluation and design-in time.
• Smart, low overhead hardware debugger circuit gives you complete control over the iniDSP system for on-chip real time debugging.
• Evaluation platform available

Block Diagram

Deliverables

• VHDL or Verilog RTL Source Code
• Functional Testbench
• Synthesys Script
• Data Sheet
• User Guide
• Hotline Support by means of phone, fax and e-mail

Technical Specifications