The 18-bit Pipeline DSP slice IP Core provides the best utilization of device resources like memory, I/O, processor and clock. It is based on pipelining technique which uses instruction level parallelism within a single processor.
18-Bit Pipeline DSP Slice IP
Overview
Key Features
- Timing resolution: 80ps
- Operating frequency range: 160MHz – 700 MHz
- Lock time: 11 cycles
- Generates user configurable precise phase shifts from 00 to 3600 with a resolution of 10
- Delays multiple periodic or aperiodic signals independent of voltage and temperature.
Benefits
- It support many independent functions, including multiplier, multiplier accumulator (MAC), multiplier-adder, higher bit adder, 3-input adder, barrel shifter, wide bus multiplexers, magnitude comparator, and counter. It also supports connecting multiple DSP slices IP Core to form wide math functions, DSP filters, and complex arithmetic. The architectural highlights of 18-bit Pipeline DSP slice IP core are as follows:
Block Diagram
