NMEA Time of Day (ToD) Master core

Overview

NetTimeLogic’s Time Of Day (ToD) Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize a Time of Day sink via NMEA over UART. The whole message creation, algorithms and calculations are implemented in the core, no CPU is required. This allows running NMEA synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface. This core only uses the second part of the clock, frequency and sub-second offset distribution shall be done in a combination with the PPS Master Clock.

All calculations and corrections are implemented completely in HW.

Key Features

Time of Day Master Clock
Built-in UART transmitter with configurable baud rate
NMEA message creator
Support for NMEA GPZDA messages for time distribution
Hardware time conversion from seconds since midnight 1.1.1970 (Linux, TAI, PTP) into Time of Day format (hh:mm:ss dd:mm:yyyy)
Sending at the local second overflow
Local time can be set via registers
In combination with a PPS Master Clock from NetTimeLogic: synchronization accuracy: +/- 25ns
AXI4 Light register set or static configuration

Benefits

Coprocessor handling NMEA synchronization standalone in the core.
Simple interface

Block Diagram

Applications

Distributed data acquisition
Ethernet based automation networks
Automation
Robotic
Automotive
Test and measurement

Deliverables

Source Code (not encrypted, not obfuscated)
Reference Designs
Testbench with Stimulifiles
Configuration Tool
Documentation

Technical Specifications

Availability

Now

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