BitBLT Graphics Hardware Accelerator (AXI Bus)

Overview

The Digital Blocks DB9100AXI3 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).

The DB9100AXI3 also contains a Monochrome Bitmap Color Expansion feature, typically used for font expansion of compressed character bitmaps. A 1-bit depth bitmap is expanded to one of two colors, a foreground or background color, with the foreground color representing the text, and the background color the non-text background.

The DB9100AXI3 also contains a programmable Alpha Blend unit, blending two bitmaps into one.

The DB9100AXI3 interfaces to a microprocessor and frame buffer memory via the AMBA AXI Interconnect, providing high performance memory throughput. The DB9100AXI3 contains a DMA Command Linked-List Processing Unit, for independently reading and processing graphics commands from the host processor.

Key Features

  • Bit Block Transfer – 3 Independent Memory Sources of data:
    • On-Screen & Off-Screen Data Block (SRC)
    • Off-Screen Fixed Pattern Data Block (PTN)
    • On-Screen visible Data Block (DST)
  • 2D Raster Operations (ROP) performed on Block Transfers:
    • 256 Raster Operations
    • ROP0, ROP1, ROP2, & ROP3 operations
    • Includes industries most popular 16 ROPs
  • BitBLT Draw Features:
    • Pixels, Horizontal & Vertical Lines
    • Overlapping & Non-Overlapping Block Transfers
    • Solid Color Block Fills
    • FONT Monochrome Bitmap to Color Expansion, either Transparent or Opaque
    • Rotation Block Transfers: 0, 90, 180, 270 degrees
    • Block Stretch on X & Y Axis
    • Alpha Blending
    • Sprite Moves
  • 2D Graphics Rendering Engine (Option):
    • Pixel Drawing
    • Line (Vector) Drawing – any direction
    • Polygon Rendering
    • Filled Polygon
  • Command FIFO or Link-List Display Processing Unit
  • Frame Buffer & Display Features Supported
    • Display Resolutions 4K x 4K
    • 8, 16 , 24, & 32 bits-per-pixel color depths
  • Interrupt Controller with 3 sources of internal interrupts with masking control
  • Reference Software Driver Included
  • On-Chip Interconnect Compliance - AXI3, AXI4, AHB, Avalon
  • Compatible with Digital Blocks DB9000 Family of TFT LCD Controller IP Cores and Reference Designs
  • Fully-synchronous, synthesizable Verilog RTL core

Benefits

  • The DB9100 family of BitBLT Graphics Hardware Accelerator IP Cores provides a higher graphics performance than a Host Microprocessor, while offering higher software productivity.

Block Diagram

BitBLT Graphics Hardware Accelerator (AXI Bus) Block Diagram

Deliverables

  • Verilog RTL Source or technology-specific netlist.
  • Comprehensive testbench suite with expected results.
  • Synthesis scripts.
  • Installation & Implementation Guide.
  • Technical Reference Manual.

Technical Specifications

Foundry, Node
IBM, TMSC, UMC, Tower, Fujitsu, GlobalFoundries, STMicroelectronics, SMIC, Common Platform
Maturity
Successful in Company FPGA Kit Demo Reference Design, Customer Products
Availability
Immediately
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Semiconductor IP