Constant False Alarm Rate Processor (CFAR)

Overview

Key Features

• Single clock cycle processing per bin making it suitable for interfacing with Pipelined FFT cores.
• Parameterised input I/Q sample bit widths
• Single clock cycle sorting update algorithm for extracting ordered statistics;
• Real-time (per block) configuration of algorithm parameters;
• Parameterised input linear power samples (max 64 bits).
• Version for logarithmic domain for reduced area and power use
• Generalised Ordered Statistic (GOS) CFAR algorithms
• GOS Cell Averaging (CA) – CFAR;
• GOS Greatest Of (GO) – CFAR;
• GOS Smallest Of (SO) – CFAR;
• Cell Averaing (CA) CFAR algorithms
• Classical CA – CFAR;
• Greatest of (GO) CA - CFAR;
• Smallest of (SO) CA – CFAR;
• Cell Averaging Statistic Hofele (CASH) CFAR algorithms
• Concurrent operation of CASH/CA-CFAR core and GOS-CFAR core
• Conversion of linear input power samples in log2 (16-bit) domain
• Real-time configuration of algorithm parameters.
• Equivalent processing in logarithmic domain for reduced area and power use.
• AMBA 4 APB/AXI4-streaming interface

Benefits

• Removes a compute intensive task away from the microprocessor to a predictable, low-latency offload engine
• Enables more radar elements to be processed for greater driver security
• Portable to either ASIC or FPGA target architecture
• Silicon proven in ISO-26262 certified products

Block Diagram

Applications

• Automotive driver assistance radar
• Roadside traffic management radar
• Military radar

Deliverables

• RTL
• Testbench
• Synthesis scripts
• Documentation
• MATLAB and C++ bit exact model
• CUDA accelerated bit exact model

Technical Specifications