Scalable and Programmable Co-processor

Overview

Key Features

• Hardware scalability to offer the best cost-performance trade-off
• Hardware complexity can be adapted to the application
• Low power solution (specialized hardware operator to reduce the power consumption)
• Highly parallel single instruction multiple data (SIMD) processor architecture
• Programmable Software-defined solution for flexible DSP components
• Flexible signal processing circuits with reduced development effort (20x lower than hard-wired design)
• Programmable Software signal processing core that avoids the development of dedicated hard-wired accelerators
• Easy support of standard revisions
• Easy product maintenance
• Easy design of multi-standard applications (multi-standard support: 4G/5G, LTE, DVB-T2, DVB-S2, …)
• Enables complex DSP and high data-rate communication system design
• Complex DSP algorithms management
• Complex vector processing optimization
• Very high system performance and computing power
• Can be optimized for FPGA and ASIC targets
• Easy migration from FPGA to ASIC
• FPGA prototyping before tape-out

Benefits

• Pulsar DSP IP Core offers THE most flexible and reliable solution for the design of complex high-end signal processing electronic circuits

Block Diagram

Deliverables

• Pulsar RTL hardware design in synthesizable VHDL code
• Pulsar C++ bit and cycle accurate model available for very fast C++/VHDL/Verilog simulation (1000 time faster than synthesizable VHDL model)
• Associated development tools, comprising starting libraries, Makefile add-ons, sample codes and simulation platform

Technical Specifications