LVDS IP

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Compare 220 LVDS IP from 38 vendors (1 - 10)
  • Ultra-low leakage I/O Library in TSMC 22nm
    • A TSMC 22nm Wirebond I/O Library with ultra-low leakage 1.8V GPIO, 1.8V I2C ODIO, 1.8V analog cell and associated ESD.
    • This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD.
    • The library has a GPIO and an ODIO. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor.
    Block Diagram -- Ultra-low leakage I/O Library in TSMC 22nm
  • 2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
    • AD_SLVS_LVDS is a highly configurable 2Gbps transceiver for LVDS or SLVS interfaces. With features like dynamic interface selection, on-die termination and pre-emphasis, this I/O is flexible enough for any system.
    • To compliment this I/O, the vendor also offers a accompanying silicon-proven ESD and GPIO pad library in TSMC 12/16nm.
    • This I/O provides 2kV HBM protection but can be extended up to 8kV upon request.
    Block Diagram -- 2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
  • LVDS Transceiver in TSMC 28nm
    • This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power differential signaling with superior signal integrity.
    • Engineered with 1.8V thick oxide devices and a 0.8V standard core interface, it operates ef- ficiently across a wide temperature range (-40°C to 125°C).
    Block Diagram -- LVDS Transceiver in TSMC 28nm
  • 1.8V/3.3V Switchable GPIO with I2C, HDMI, LVDS, ESD & Analog in TSMC 28nm
    • A TSMC 28nm HPM/HPC/HPC+ Wirebond I/O Library with a switchable 1.8V/3.3V GPIO, 5V I2C ODIO, 1.8V & 3.3V Analog Cells, ESD and more.
    • A key attribute of this silicon-proven library is to detect and adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    • The GPIO can be configured as input, output, open-source, or open-drain with an optional 60kohm pull-up or pull-down resistor.
    Block Diagram -- 1.8V/3.3V Switchable GPIO with I2C, HDMI, LVDS, ESD & Analog in TSMC 28nm
  • HDMI, LVDS, RF and Analog Pads in TSMC 45/40nm
    • A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.
    • This library is collection of analog only IO and Power/Ground pads that include ESD. The target applications are high performance analog interfaces including HDMI, RF, LVDS, basic analog and other applications.
    • The pads include a host of specialty features including fail safe, low capacitance, high ESD protection, and IEC robustness.
    Block Diagram -- HDMI, LVDS, RF and Analog Pads in TSMC 45/40nm
  • 2.5V GPIO with 2Gbps LVDS RX TX and Analog Cell in GlobalFoundries 65nm LPe
    • A GlobalFoundries 65nm LPE Wirebond I/O library with 2.5V GPIO, 2Gbps LVDS TX RX and 2.5V Analog/RF cell with associated ESD.
    • A key attribute of this silicon-proven library include dual selectable drive strengths and independent input & output enable / disable.
    • The GPIO cell can be configured as input, output or open-drain with a Schmitt trigger input and selectable internal 60K ohm pull-up or pull-down resistor.
    Block Diagram -- 2.5V GPIO with 2Gbps LVDS RX TX and Analog Cell in GlobalFoundries 65nm LPe
  • GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
    • The 2.5Gbps LVDS transceiver in GlobalFoundries LP/LP+ is designed for high-speed, low-power data transmission in radiation-intensive environments.
    • Engineered with a Rad-Hard by Design approach, the Rad-Hard cells have been proton tested to 64 MeV with a flux exceeding 1.3E+09, and is latch-up proven to 200mA across -40C to 125C, ensuring robust immunity against TID, SEE, and SEL effects.
    Block Diagram -- GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
  • GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
    • This SLVS I/O Library delivers a robust, high-performance solution for high-speed differential signaling in GlobalFoundries 12nm process technology.
    • Designed for optimal signal integrity, this 0.8V SLVS transceiver features fast rise and fall times, low propagation delay, and built-in pre-emphasis to enhance signal quality over longer traces.
    • With support for data rates up to 3Gbps, it enables reliable, low-power communication while maintaining excellent noise immunity.
    Block Diagram -- GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
  • LVDS I/O IP - High Frequency Transceiver
    • The Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission.
    • Typical LVDS I/O applications include displays, printers, and other high-speed data interfaces.
    • This LVDS IP includes a transmitter, receiver, and a novel equalization design supporting programmable pre-emphasis at the transmitter. 
    Block Diagram -- LVDS I/O IP -  High Frequency Transceiver
  • High-speed LVDS (Low-Voltage Differential Signaling) transceiver
    • Compatible with ANSI/TIA/EIA 644-1995 LVDS standard
    • Multi-channel LVDS transceiver function
    • Maximum data transfer rate: 992Mbps (496MHz)
    • Typical output voltage: 350mV (100-Ω load)
    Block Diagram -- High-speed LVDS (Low-Voltage Differential Signaling) transceiver
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