ESD Protection IP

Compare 145 ESD Protection IP from 8 vendors (1 - 10)

1.8V general purpose I/O for 4nm FinFET
- Enable higher voltage operation, beyond the foundry IO levels
- Easily replace existing I/O cells
- Integrated scalable ESD protection
- Bias circuit can be shared with multiple I/Os
3.3V general purpose I/O for 28nm CMOS
- Enable higher voltage operation, beyond the foundry IO levels
- Easily replace existing I/O cells
- Integrated scalable ESD protection
- Bias circuit can be shared with multiple I/Os
Power and Ground BondPads that include CC-100IP Digital and Switching Circuit Power Reduction Technology, Featuring 20% to 40% Total Dynamic Power Reduction
- 20% to 40% Digital and Dynamic Power Reduction
- Fits into any IC bondpad
1.0-3.3V GPIO With I2C Open Drain And 3.3V & 5V Analog Cells in 55nm
- 1.0V-3.3V | 3.3V IO operation
- Dual independent IO rails
- Output enable / disable (HiZ when disabled)
- Power-down control (HiZ upon VDD disable)
A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
- GPIO:
- ANALOG
- OTP Programming Cell
- Physical Attributes
1.8V/3.3V Switchable GPIO With 5V I2C Open Drain & Analog in 16/12nm
- Multi-voltage 1.8V / 3.3V switchable operation
- 4 selectable drive strengths (25-235MHz @1.8V, 10pF)
- Full-speed output enable
- Independent power sequencing
A 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC
- Fail-Safe GPIO in TSMC 28nm process technology
- Physical features
- This library also features a 33MHz OSC (3.3V).
LVDS IO Pad Set
- Powered from 1.8V ±10% and 1.0V (±10%) to 1.1V (-10%/+5%) core power supplies
- Operates up to 1.2GHz (2.4Gbps)
- Input receive sensitivity of 75mV peak differential (without hysteresis)
- Common mode range from 0V to 2.4V (limited by Power Supply)
High voltage tolerant I/O
- Scalable robustness
- Area efficient
- low capacitance option
Small area rail clamp for FinFET
- Power clamp ESD solutions
- Rail clamp ESD protection
- 0.75V domain