A 1.8V/3.3V flip-chip I/O library with ESD-immune GPIOs and integrated POC circuitry in TSMC FFC/FFC+.
This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic. It includes support cells for all power domains: 0.8V, 1.8V, and I/Oand incorporates latch-up immune, JEDEC-compliant ESD structures. The library is designed for flip-chip packaging and includes vertical and horizontal variants to support all die edge orientations. All power domains include integrated power-on control (POC) cells for safe and reliable sequencing.
Operating Conditions
| Parameter | Value |
| VDDIO | 1.8V / 3.3V +/-10% |
| Core VDD | 0.8V +/-10% |
| Tj | -40°C to 125°C |
Cell Size and Metal Stack
| Cell Size | Metal Stack |
| MH_IO | 25um x 53um |
| MH_VDDIO_POC | 50um x 53um |
| Metal Stack | 1P9M |
Library Cell Summary
| Cell Type | Feature |
| MH_IO | 1.8V/3.3V GPIO, 2-bit drive strength |
| MH_VDDIO_ | POC POC and ESD protection |
| MH_VDD / VDD18 | 0.8V / 1.8V power cells w/ ESD |
| MH_CORNER | Power continuity at pad corner |
