USB Phy IP

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Compare 321 USB Phy IP from 21 vendors (1 - 10)
  • USB 2.0 PHY IP core
    • Complies with USB specifications, rev. 2.0 and 1.1
    • Complies with UTMI+ specification, level 3, rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
    Block Diagram -- USB 2.0 PHY IP core
  • High Speed Inter-CHIP USB 2.0 PHY
    • High-Speed 480Mbps data rate only
    • Source-synchronous serial interface
    • No power consumed unless a transfer is in progress.
    • Maximum trace length of 10cm
    Block Diagram -- High Speed Inter-CHIP USB 2.0 PHY
  • USB2.0 Host Transceiver
    • Fully compliant with latest USB 2.0
    • Innovative technique to recover clock from 480 Mbps data.
    • High frequency PLL.
    • Advanced High-Speed Transmitter and Receiver.
    Block Diagram -- USB2.0 Host Transceiver
  • USB 2.0 Device Transceiver
    • Fully compliant with latest USB2.0 spec version 2.0.
    • Innovative technique for clock recovery from 480 Mbps data.
    • High frequency PLL.
    • Advanced high-speed transmitter and receiver.
    Block Diagram -- USB 2.0 Device Transceiver
  • USB3.2 PHY & Controller
    • USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications
    • Innosilicon provides a comprehensive set of software drivers to support commonly used USB peripherals
    • In addition, our established USB ecosystem—comprising USB silicon suppliers, design IP houses, and verification and testing vendors—helps reduce development and production costs for USB host and peripheral manufacturers
    Block Diagram -- USB3.2 PHY & Controller
  • USB2.0 PHY(HSIC/Host/Device/OTG/Hub)/ eUSB PHY
    • USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications
    • Innosilicon provides a comprehensive set of software drivers to support commonly used USB peripherals
    • In addition, our established USB ecosystem—comprising USB silicon suppliers, design IP houses, and verification and testing vendors—helps reduce development and production costs for USB host and peripheral manufacturers
    Block Diagram -- USB2.0 PHY(HSIC/Host/Device/OTG/Hub)/ eUSB PHY
  • USB PD Synthesizable Transactor
    • USB PD Features
    • Supports USB Power Delivery Specification 3.1,3.0, 2.0 and 1.0
    • Supports USB Type-C Cable and Connector Specification
    • Supports Cable plug communication
    Block Diagram -- USB PD Synthesizable Transactor
  • USB 3.1 PHY
    • Supports USB 3.1, PCIe 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII
    • Multi-protocol support for simultaneous independent links
    • Supports SRIS and internal SSC generation
    • Supports PCIe L1 sub-states
    • Automatic calibration of on-chip termination resistors
    Block Diagram -- USB 3.1 PHY
  • USB 2.0 PHY
    • Designed to the USB 2.0 specification, and operates at High Speed (480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps)
    • Complies with the UTMI v1.05 specification
    • Multiple reference clock supported from 9.6MHz up to 52MHz
    • 8-bit 60MHz and 16-bit 30MHz parallel interfaces
    • Battery Charging Specification v1.2
    Block Diagram -- USB 2.0 PHY
  • eUSB2V2 PHY
    • Up to 4.8Gbps scalable data rate
    • Compliant to eUSB2V2 r1.0 / UTMI2.0 r0.9
    • Configurable to Host or Peripheral
    • Supports L1/L2 low power state
    • Supports eUSB2V2 Compliance Modes and RxMargining Mode
    • Support 19.2/24/48/100 MHz Ref Clocks
    Block Diagram -- eUSB2V2 PHY
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