USB PD Synthesizable Transactor

Overview

Key Features

• USB PD Features
• Supports USB Power Delivery Specification 3.1,3.0, 2.0 and 1.0
• Supports USB Type-C Cable and Connector Specification
• Supports Cable plug communication
• Supports all Resets: Hard, Soft and Cable Resets
• Supports all types of packets
• Supports BFSK and BMC signaling of physical layer
• Supports BIST
• Supports Cable plug communication
• Supports Timer as per specification
• Supports Counters as per specification
• Supports data role swap and power role swap
• Supports Structured and Unstructured VDM
• Supports Device and System Policy
• Supports injecting timing variations in physical layer
• Supports Error Injection
• CRC error
• Message type errors
• FIFO depth programmable
• Auto response generation
• Supports all Swappings: Power role, Data role, Fast power role and Vconn swap
• Supports chunked transaction
• Supports included extended power supply capabilities and status
• Notifies the test bench of significant events such as transactions, warnings, and protocol violations
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• TYPE-C Features
• Supports USB Type-C Cable and Connector Specification 3.0,2.0 and 1.0
• Supports Debug accessory operation
• Supports Audio accessory operation
• Supports Plug Orientation/Cable Twist Detection
• Supports all the connection fsm states

Benefits

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram



Deliverables

• Synthesizable transactors
• Complete regression suite containing all the USB Power Delivery testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and function's used in verification env
• Documentation contains User's Guide and Release notes

Technical Specifications