USB3.2 PHY & Controller

Overview

USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications. Innosilicon provides a comprehensive set of software drivers to support commonly used USB peripherals. In addition, our established USB ecosystem—comprising USB silicon suppliers, design IP houses, and verification and testing vendors—helps reduce development and production costs for USB host and peripheral manufacturers.

The USB 3.2 PHY is a highly programmable module that converts high-speed serial data into parallel data, compliant with the PIPE standard. The PHY supports USB 3.2 Gen 2x2, delivering SuperSpeed data rates of up to 20Gbps. Streamlined production testing is enabled through built-in self-test (BIST), multiple loopback modes, and boundary scan. Its modular and flexible design ensures compatibility with the latest USB Type-C configurations, integrating all necessary I/Os and ESD protection in a single drop-in block. Like all Innosilicon IPs, our USB 3.2 solution is fully customizable, enabling seamless integration and optimization for your specific application requirements.

Key Features

  • Supports 20Gb/s serial data transmission rate
  • Utilizes a 16-bit or 32-bit interface to transmit and receive USB SuperSpeed data
  • Allows integration of high speed components into a single functional block.
  • Data and clock recovery from serial stream on the USB Enhanced SuperSpeed bus
  • Holding registers to stage transmit and receive data
  • Supports direct disparity control for use in transmitting compliance pattern
  • 8b/10b, 128/132b encode/decode and error indication
  • Receiver detection
  • Low Frequency Periodic Signaling (LFPS) Transmission
  • Built in self-test and loopback test
  • Selectable Tx Margining, FFE and signal swing values
  • Selectable Rx CTLE peaking range and DFE taps
  • Auto calibrated and tunable on die termination (ODT)
  • Integrated IO with ESD protection aimed at HBM 2KV and CDM 250V
  • Well-tuned T-coil to promote ultra-high bandwidth

Benefits

  • Small die size
  • Low pin counts
  • Low power consumption
  • Fully customizable

Block Diagram

USB3.2 PHY & Controller Block Diagram

Applications

  • Enterprise Computing
  • Storage Networks
  • Network-on-Chip (NoC)
  • Automotive
  • Server Connectivity
  • GPU Interfacing

Deliverables

  • Verilog Sim Behavioral simulation model for the PHY
  • Encrypted IO spice netlist for SI evaluation
  • Integration Guidelines
  • Test Guidelines
  • GDSII Layout and layer map for foundry merge
  • Place and Route LIB and LEF views for the AFE
  • LVS and DRC verification reports

Technical Specifications

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Semiconductor IP