USB 2.0 PHY

Overview

Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power

Architected to quickly and easily integrate into any SoC, the Cadence^® USB 2.0 On-The-Go (OTG) PHY IP connects seamlessly to a Cadence or third-party UTMI-compliant controller. The IP provides you with a cost-effective, low-power solution for demanding applications. It offers SoC integrators the advanced capabilities and support that exceed the requirements of high-performance designs and implementations. The Cadence USB 2.0 OTG IP is silicon-proven and has been extensively validated with multiple hardware platforms.

Key Features

Designed to the USB 2.0 specification, and operates at High Speed (480Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps)
Complies with the UTMI v1.05 specification
Multiple reference clock supported from 9.6MHz up to 52MHz
8-bit 60MHz and 16-bit 30MHz parallel interfaces
Battery Charging Specification v1.2
Supports link power management (LPM)
APB and JTAG interface

Benefits

Silicon-Proven Solution with USB IF Certification: Mature IP with proven mass production history
Low-Power Design Enables Power-Saving Applications: Low active power consumption with small footprint
Extensive Test Features Provide Improved Production Testing Experience: Comprehensive test features include datapath loopback, scan, BIST, bypass

Block Diagram

Deliverables

Verilog behavioral modules for PHY module
Verilog testbench with configuration files and sample tests
Liberty timing model
Layout abstract in LEF format
GDSII with flat netlist for LVS

Technical Specifications

TSMC

Silicon Proven: 7nm , 12nm , 16nm

Request Info