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PCI Express Phy IP

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Compare 297 PCI Express Phy IP from 24 vendors (1 - 10)
  • PCIe 6.0 / CXL 3.0 PHY & Controller
    • Innosilicon’s PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and PIPE specifications
    • These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, data centers, cloud servers, AI and machine learning, storage expansion, and high-speed interconnect applications
    Block Diagram -- PCIe 6.0 / CXL 3.0 PHY & Controller
  • PCIe 5.0/4.0/3.0 PHY & Controller
    • Innosilicon’s PCIe 5.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 5.0/4.0/3.0, and PIPE specifications
    • These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, storage networks, automotive, and I/O connectivity applications
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    Block Diagram -- PCIe 5.0/4.0/3.0 PHY & Controller
  • PCIe GEN6 PHY IP
    • The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for high-speed data transfer.
    • It supports advanced applications, including AI/ML, High-Performance Computing, and next-generation storage solutions.
    Block Diagram -- PCIe GEN6 PHY IP
  • PCIE 6.0/5.0/4.0/3.0/2.0
    • Support PCI Expression Gen5 & Gen4 & Gen3 & Gen2 & Gen1
    • Configurable differential voltage swing
    • Embedded low jitter LC PLL with fixed bandwidth and output frequency
    • PLL Frequency Lock detection
    Block Diagram -- PCIE 6.0/5.0/4.0/3.0/2.0
  • PCI Express Synthesizable Transactor
    • Supports PCI Express specs 1.0/2.0/3.0/4.0/5.0/6.0.
    • Supports MPCIE
    • Supports PIPE, PCS/PMA, and serdes interface
    • Supports MPHY RMMI and serial Interface
    Block Diagram -- PCI Express Synthesizable Transactor
  • PHY for PCIe 6.0 and CXL
    • Architecture optimized for HPC, AI/ML, storage, and networking
    • Ultra-long reach, low latency, and low power
    • Advanced DSP delivers unmatched performance and reliability
    • Comprehensive real-time diagnostic, monitor, and test features
    • Bifurcation support for x1, x2, x4, x8, and x16 lanes
    Block Diagram -- PHY for PCIe 6.0 and CXL
  • PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
    • Wide range of protocols that support networking, high-performance computing (HPC), and applications
    • Low-latency, long-reach, and low-power modes
    • Multi-Link PHY—mix protocols within the same macro
    • EyeSurf —non-destructive on-chip oscilloscope
    • User-friendly graphical interface provides easy access to embedded bit-error-rate (BER) and pattern testers and monitors to measure the link performance in real time
    Block Diagram -- PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
  • PHY for PCIe 3.1
    • Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII
    • Multi-protocol support for simultaneous independent links
    • Supports SRIS and internal SSC generation
    • Supports PCIe L1 sub-states
    • Automatic calibration of on-chip termination resistors
    • Supports internal and external clock sources with clock active detection
    Block Diagram -- PHY for PCIe 3.1
  • PHY for PCIe 5.0 and CXL
    • Low-latency, long-reach, and low-power modes
    • Wide range of protocols that support networking, storage, and computing applications
    • Advanced equalization and clock-data-recovery to deliver unmatched channel loss handling performance and reliability
    • Eye Surf —provides convenient access to an integrated non-destructive real-time eye scope and BER bathtub curve to monitor the bit error rate (BER) and the link performance during live traffic
    Block Diagram -- PHY for PCIe 5.0 and CXL
  • PCI Express 4.0 PHY
    • Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 specifications
    • Supports all power-saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 specifications
    • Supports L1 PM/CPM substates with CLKREQ#
    • Supports the separate REFCLK Independent SSC (SRIS) architecture
    Block Diagram -- PCI Express 4.0 PHY
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