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PCI Express IP

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Compare 483 PCI Express IP from 45 vendors (1 - 10)
  • ULL PCIe DMA Controller
    • The ULL PCIe DMA Controller is a high-performance, bidirectional data transfer solution. It is designed for seamless communication between FPGAs and host CPUs over PCIe.
    • With a round-trip time as low as 585ns*, this IP core empowers developers to maximize resource utilization and achieve ultra-low latency without compromising performance.
    Block Diagram -- ULL PCIe DMA Controller
  • PCIe - PCI Express Controller
    • The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard.
    • It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.
    Block Diagram -- PCIe - PCI Express Controller
  • PCI Express PIPE PHY Transceiver
    • Supports 2.5Gb/s serial data rate
    • Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
    • Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
    • Data and clock recovery from serial stream on the PCI Express bus
    Block Diagram -- PCI Express PIPE PHY Transceiver
  • L/H-Tile PCIe Hard IP
    • Stratix® 10 FPGAs incorporate the L/H-Tile chiplets which include a configurable, hardened protocol stack for PCIe that is compliant with PCIe Base Specification 3.0
    • This Avalon® Streaming Interface Hard IP supports PCIe 1.0, 2.0, and 3.0 data rates and x1, x2, x4, x8, or x16 configurations, including support for SR-IOV functionality.
    Block Diagram -- L/H-Tile PCIe Hard IP
  • P-Tile PCIe* Hard IP
    • P-Tile is an FPGA companion tile available on Stratix® 10 DX and Agilex™ 7 FPGA F-Series device that natively supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass Modes.
    Block Diagram -- P-Tile PCIe* Hard IP
  • Scalable Switch Intel® FPGA IP for PCI Express
    • The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream port and connectivity for up to 64 downstream ports.
    Block Diagram -- Scalable Switch Intel® FPGA IP for PCI Express
  • Intel® Arria® 10 and Intel® Cyclone® 10 PCIe Hard IP
    • Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with the PCI Express Base Specification 3.0 and PCI Express Base Specification 2.0 respectively
    • The hard IP provides the Avalon® Streaming (Avalon-ST) interface and can be configured for either Rootport (RP) or Endpoint (EP) modes.
    Block Diagram -- Intel® Arria® 10 and Intel® Cyclone® 10 PCIe Hard IP
  • F-Tile PCIe Hard IP
    • The F-Tile Intel® Hard IP supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass Modes
    • F-Tile serves as a companion tile for Agilex™ 7 devices.
    Block Diagram -- F-Tile PCIe Hard IP
  • GTS PCIe Hard IP
    • Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 4.0 x8 configurations for Root Port (RP), Endpoint (EP), and Transaction Layer (TL) bypass modes.
    • GTS PCIe Hard IP for PCI Express Greatly Simplifies Design Integration for a Broad Range of Applications
    Block Diagram -- GTS PCIe Hard IP
  • GTS PMA/FEC Direct PHY IP
    • GTS is a general purpose transceiver in Agilex™ 5 and Agilex™ 3 FPGAs
    • The transceiver is monolithically integrated into the FPGA core fabric offering up to 28Gbps for Agilex™ 5 and up to 12.5Gbps data speeds for Agilex™ 3 FPGA
    • The transceiver is optimized for power efficiency, low-latency, and dynamic reconfiguration to implement multiple protocols.
    Block Diagram -- GTS PMA/FEC Direct PHY IP
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