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Verification IP for PCIe

Overview

Accelerated confidence in simulation-based verification of RTL designs with PCI Express (PCIe) interfaces: PCIe Gen2/3/4/5/6/7

Avery PCI Express (PCIe) VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates constrained random traffic generation, robust TL/DLL/PHY layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debugging and performance analysis metrics.

With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests and work on more complex topologies, such as bifurcation. Avery compliance test suites offer effective core through chip-level tests, including those used in compliance workshops as well as extended tests developed by Avery to cover the specification features.

Key Features

  • Comprehensive PCIe® standard support, including:
    • PCIe 6.0, 5.0r1, 4.0, 3.1a
    • PIPE 6.0, 5.2.1, UCIe 1.0
  • Root complex, endpoint, SR-IOV endpoint, re-timer, PHY agents, and PIPE-to-PIPE and UCIe RDI box virtual interfaces
  • PCIe 6.0 support, including:
    • 64 GT/s speed, PAM4
    • FLIT mode support
    • TLPs, DLLPs, OS
    • FEC and CRC enhancements
  • PCIe 5.0 supports new features, including:
    • New Gen5 EIEOSQ
    • Gen5 TS1/TS2 enhanced link behavior control bits
    • Physical layer 32.0 GT/s extended capability
    • Equalization updates
      • Full equalization, bypass, no equalization UCIe 1.0 die to die chiplet interface with RDI2RDI box.
  • CXL 1.1/2.0/3.0 ready
  • New UCIe supports logic PHY and RDI-to-RDI box
  • UCIe 1.0 die to die chiplet interface with RDI2RDI box
  • PCI-SIG® compliance checklist coverage to isolate DUT bugs faster
  • PCI-SIG based and Avery-built compliance test suites
  • Random DUT configuration for improved interoperability testing
  • Multi-function queues to facilitate modeling high bandwidth, interleaved, and delayed traffic requests and completions
  • QEMU/PCIe RC integration supporting virtual host platform for running Linux OS, kernel drivers, and benchmarking programs

Benefits

  • Provides a comprehensive UVM verification solution
  • Boosts verification efficiency
  • Enables development of more complex tests and more complex topologies
  • Increases effectiveness with core-through-chip-level tests
  • Generates tracker reports showing packet flow

Block Diagram

Verification IP for PCIe Block Diagram

Deliverables

  • PCIe Gen1-6 dual mode RC/EP, Retimer, and PIPE PHY and optional UCIe PHY driver BFMs
  • Compliance test suites
  • User guide

Technical Specifications

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Verification IP for PCIe
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