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ESD Protection IP for TSMC

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Compare 43 ESD Protection IP for TSMC from 2 vendors (1 - 10)
  • ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
    • A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
    • This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications.
    • Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications.
    Block Diagram -- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
  • High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
    • A 3.3V wirebond I/O library with 8kV HBM ESD protection, a 1.2Gbps LVDS, GPIO, and I2C compliant ODIO in an ultra-small footprint.
    • This library ensures robust reliability in challenging environments, with capabilities including 8kV HBM, 500V CDM, and a robust 2kV IEC 61000-4-2 system stress capability.
    • Its compact footprint makes it ideal for applications where size is critical.
    Block Diagram -- High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
  • A 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC
    • Fail-Safe GPIO in TSMC 28nm process technology
    • Physical features
    • This library also features a 33MHz OSC (3.3V).
    Block Diagram -- A 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC
  • LVDS IO Pad Set
    • Powered from 1.8V ±10% and 1.0V (±10%) to 1.1V (-10%/+5%) core power supplies
    • Operates up to 1.2GHz (2.4Gbps)
    • Input receive sensitivity of 75mV peak differential (without hysteresis)
    • Common mode range from 0V to 2.4V (limited by Power Supply)
    Block Diagram -- LVDS IO Pad Set
  • 5V I/O and ESD in TSMC 12nm FFC/FFC+
    • A 5V Library for Generic I/O and ESD Applications TSMC 12NM FFC/FFC+ process.
    • This library is a base set of ESD protection structures for I/O and Power supplies. The design targets up to 8A applications (>8kV HBM).
    • The I/Os are designed to trigger and protect interfaces during Electrical Overstress (EOS) events during normal operation.
  • 1.8V General Purpose I/O Pad Set
    • Bidirectional GPIO Driver Features
    • In full-drive mode, this driver can operate to frequencies in excess of 100MHz with 15pF external load and 125 MHz with 10pF load. Actual frequency limits are load and system dependent. A maximum of 200 MHz can be achieved under small capacitive loads.
  • I3C I/O Library
    • Supported I3C operating modes:
    • In open-drain modes, this cell requires a pull-up to a high voltage power supply (VDDP). The sizing of an external resistor or appropriate pull-up network is application dependent.
  • 1.2V GPIO library designed for the SVID three-line interface.
    • Open drain operation only
    • Operating frequency – up to 25MHz
    • Fault-tolerant to 1.32V at PAD (no current flow when DVDD = 0V)
    • Output enable
  • 1.2V GPIO
    • ESD Protection
    • Latch-up Immunity:
  • 1.8V General Purpose Staggered I/O Pad Set
    • Bidirectional GPIO Driver Features
    • ? Multi-Voltage (1.2V, 1.5V, 1.8V)
    • ? LVCMOS / LVTTL input with selectable hysteresis
    • ? Programmable drive strength (rated 2mA to 12mA)
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