LVDS IO Pad Set

Overview

The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers operating at data rates up to 2.4 Gbps. The pad set includes a full complement of power, spacer, and adapter cells to assemble a complete pad ring by abutment. An included rail splitter allows isolated LVDS domains to be placed in the same pad ring with other power domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.

Key Features

Powered from 1.8V ±10% and 1.0V (±10%) to 1.1V (-10%/+5%) core power supplies
Operates up to 1.2GHz (2.4Gbps)
Input receive sensitivity of 75mV peak differential (without hysteresis)
Common mode range from 0V to 2.4V (limited by Power Supply)
Power-up sequence independent
Power consumption is 1.8 mW typical and 5 mW maximum

Block Diagram

Deliverables

a. Physical abstract in LEF format (.lef)
b. Timing models in Synopsys Liberty formats (.lib and .db)
c. Calibre compatible LVS netlist in CDL format (.cdl)
d. GDSII stream (.gds)
e. Behavioral Verilog (.v)
f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
g. Databook (.pdf)
h. Library User Guide - ESD Guidelines (.pdf)

Technical Specifications

Foundry, Node

GLOBALFOUNDRIES 28nm SLP

Maturity

Silicon Proven

Availability

Available now

GLOBALFOUNDRIES

In Production: 130nm
Pre-Silicon: 130nm
Silicon Proven: 28nm HPP , 28nm LPH , 28nm SLP , 40nm LP , 55nm , 65nm , 65nm LP , 65nm LPe , 90nm , 90nm LP , 130nm , 130nm HP , 130nm LP , 130nm LV

TSMC

In Production: 65nm GP , 90nm G , 130nm G
Pre-Silicon: 65nm GP , 90nm G , 130nm G
Silicon Proven: 55nm GP , 55nm LP , 65nm G , 65nm GP , 65nm LP , 90nm G , 90nm GT , 90nm LP , 90nm zzz

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