IP Catalog > Memory & Libraries IP > I/O Library IP > ESD Protection IP > ESD Protection

ESD Protection

Overview

The ESD Protection library provides ESD protection components. In addition to core-placeable ESD protection cells, discrete components (RF diodes and SCR’s) are provided to enable construction of a custom ESD protection solution.

This library is compatible with all 7nm library offerings.

Key Features

  • ESD Protection:
    • JEDEC compliant
      • 2KV ESD Human Body Model (HBM)
      • 500 V ESD Charge Device Model (CDM)
    • Latch-up Immunity:
      • JEDEC compliant
        • Tested to I-Test criteria of ± 100mA @ 125°C

Deliverables

  • Physical abstract in LEF format (.lef)
  • Timing models in Synopsys Liberty formats (.lib and .db)
  • Calibre compatible LVS netlist in CDL format (.cdl)
  • GDSII stream (.gds)
  • Behavioral Verilog (.v)
  • Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • Databook (.pdf)
  • Library User Guide - ESD Guidelines (.pdf)

Technical Specifications

Short description
ESD Protection
Vendor
Vendor Name
Foundry, Node
TSMC, 7nm
Maturity
Silicon Proven
Availability
Available Now
TSMC
Pre-Silicon: 7nm
Request Info

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