This 28nm GPIO is designed for high-speed (>150MHz output, >250MHz input) applications. The IO operates at either 1.8V or 3.3V and can dynamically switch between these voltages during operation. The cell is power sequence-independent and is fully self-protecting during the power ramp. A unique feature of the 28nm GPIO is its fail-safe capability. Though a full push-pull IO, the part can be powered down and leak low current from externally driven active signals, much like an open-drain IO.
Built into our IO libraries and also offered as a separate service is our strong ESD expertise. Certus was founded by ESD engineers, and our results speak for themselves. We consistently exceed 2KV HBM and 500V CDM ESD targets and provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD, and Cable Discharge Events (CDE).
Certus supports IO libraries across multiple TSMC nodes, including 180nm, 130nm, 40nm, 28nm, 22nm, and 16/12nm. Certus is particularly suited at providing custom variants in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
A 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC
Overview
Key Features
- Fail-Safe GPIO in TSMC 28nm process technology
- JEDEC LVCMOS compliant
- RGMII, SD capable
- 1.8V-3.3V dynamic multi-voltage operation
- Selectable drive strengths
- Selectable input hysteresis
- 20um pitch, 180um tall cell
- Triple-row staggered wirebond pad arrangement
- >2kV HBM, 500V CDM ESD
- Physical features
- 20um x 186um cell size
- 9 metals - 6X2Z
- 20um pitch, triple row staggered wirebond
- This library also features a 33MHz OSC (3.3V).
Benefits
- Tight cell pitch
- Small footprint triple staggered wirebond
- Fast GPIO
- Fail-Safe IO
- Power sequence independence
- Selectable input hysteresis
- Proven HBM & CDM ESD protection
Block Diagram
Applications
- General Purpose Applications
- Memory interfaces
- Open-Drain IO applications
- RGMII
- FLASH and SD Card interfaces
- UARTS
Deliverables
- GDS
- CDL netlist
- Verilog stub
- Verilog behavioral model
- LEF
- Liberty Timing Files
- IBIS (option)
- Electrical datasheet
- User guide and application notes
- Consulting and Support
Technical Specifications
Foundry, Node
28nm
Maturity
Silicon Proven
Availability
Immediate
TSMC
In Production:
28nm
HP
,
28nm
HPC
,
28nm
HPCP
,
28nm
HPL
,
28nm
HPM
,
28nm
LP
Pre-Silicon: 28nm HP , 28nm HPC , 28nm HPCP , 28nm HPL , 28nm HPM , 28nm LP
Silicon Proven: 28nm HP , 28nm HPC , 28nm HPCP , 28nm HPL , 28nm HPM , 28nm LP
Pre-Silicon: 28nm HP , 28nm HPC , 28nm HPCP , 28nm HPL , 28nm HPM , 28nm LP
Silicon Proven: 28nm HP , 28nm HPC , 28nm HPCP , 28nm HPL , 28nm HPM , 28nm LP
Related IPs
- 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- 1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (22nm)
- 1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (12nm)
- 3.3V general purpose I/O for 28nm CMOS
- OSC
- OSC