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PLL IP

Welcome to the ultimate PLL IP hub! Explore our vast directory of PLL IP

Here, you will find a variety of PLL designs and architectures, each tailored to specific application needs, including fractional-N PLLs, integer-N PLLs, and Delay-Locked Loops (DLLs). These variants offer different advantages, such as reduced phase noise, higher frequency stability, and improved design flexibility. Additionally, some advanced PLL IPs incorporate features like spread spectrum clocking to minimize electromagnetic interference, making them suitable for use in sensitive electronic environments.

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Search (1,856)
Compare 1,856 PLL IP from 53 vendors (1 - 10)
  • 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
    • Rail-to-Rail IQ ADC Input Capability
    • 65dB IQ ADC SNR
    • Programmable Full-Scale IQ DAC Output Current
    • 65dB IQ DAC SNR
    Block Diagram -- 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
  • 40nm 1.1V 6.0GHz-9.4GHz Fractional-N RF PLL
    • TSMC 40nm CMOS
    • 6.0GHz-to-9.7GHz Buffered VCO PLL Output Coverage
    • Scalable Power Consumption
    Block Diagram -- 40nm 1.1V 6.0GHz-9.4GHz Fractional-N RF PLL
  • 40nm 1.1V 2GHz-4.7GHz Fractional-N RF Quadrature PLL
    • 2.0GHz-to-4.7GHz PLL Output Coverage
    • Scalable Power Consumption
    Block Diagram -- 40nm 1.1V 2GHz-4.7GHz Fractional-N RF Quadrature PLL
  • 40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
    • 16MHz-to-2GHz PLL Output Coverage
    • Scalable Power Consumption
    • Three independent programmable PLL outputs
    • Internal Calibration Engine and Convergence Algorithm
    Block Diagram -- 40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
  • 4-Phase LC PLL on INTEL 16
    • High performance design for meeting low jitter requirements including Ref Clock applications
    • Implemented with Analog Bits’ proprietary LC architecture
    • Low power consumption
    • Integrated power supply regulation for low deterministic jitter
    Block Diagram -- 4-Phase LC PLL on INTEL 16
  • All Digital Phase Locked Loop
    • The iniADPLL is an all digital implementation of a phase locked loop. Plls are widely used in telecom applications for clock recovery, clock generation and clock supervision.
    • Different phase dtectors (FIFO fill level, phase erros, and so on) may be used and can be adapted to perfectely fit the application.
    Block Diagram -- All Digital Phase Locked Loop
  • Multi-rate Audio DAC/PLL Core
    • Operates from single 27/54MHz clock.
    • Ideal for MPEG, AC-3, DVD systems
    • Internally generates audio sample clocks
    • Multi-sample rates: 32, 44.1, 48 KHz
    Block Diagram -- Multi-rate Audio DAC/PLL Core
  • Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
    • Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
    • Entirely core voltage powered, needs no analog supply voltage
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Very fine precision: near 1 part per billion resolution
    Block Diagram -- Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
  • PLL
    • The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, risk, and cost in the development of Analog Front-End design
    • It can generate a stable high-speed clock from an ultra-wide input clock
    • With excellent supply noise immunity, the PLL is ideal for use in noisy mixed signal SoC environments
    Block Diagram -- PLL
  • Low Power 300-600 MHz programmable PLL
    • The WEAPLL400M22 is a low power integer PLL operating at a single 0.8 V power supply
    • This PLL has a wide programmable frequency range operation operating from 300 MHz up to 600 MHz
    • The VCO outputs are coming into 8 cascaded phases
    • The PLL needs a sourcing current of 2 uA in order to operate
    Block Diagram -- Low Power 300-600 MHz programmable PLL
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