Low Bandwidth PLL IP
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Low Bandwidth PLL IP
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18
Low Bandwidth PLL IP
from 5 vendors
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10)
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40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
- Rail-to-Rail IQ ADC Input Capability
- 65dB IQ ADC SNR
- Programmable Full-Scale IQ DAC Output Current
- 65dB IQ DAC SNR
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40nm 1.1V 6.0GHz-9.4GHz Fractional-N RF PLL
- TSMC 40nm CMOS
- 6.0GHz-to-9.7GHz Buffered VCO PLL Output Coverage
- Scalable Power Consumption
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40nm 1.1V 2GHz-4.7GHz Fractional-N RF Quadrature PLL
- 2.0GHz-to-4.7GHz PLL Output Coverage
- Scalable Power Consumption
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40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
- 16MHz-to-2GHz PLL Output Coverage
- Scalable Power Consumption
- Three independent programmable PLL outputs
- Internal Calibration Engine and Convergence Algorithm
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1.68 to 1.917 GHz Phase-Locked Loop
- AMS SiGe BiCMOS 0.35um
- Reference frequency from 10MHz to 125MHz
- LO1 frequency range from 1.692GHz to 1.973GHz
- LO2 frequency range from 175MHz to 225MHz
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High Quality LC-PLLs
- Automatically locks over an extremely wide input frequency range
- Dual-loop P
- Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation
- Passes PCIe6 reference clock requirements with wide margin
- Reference spur <200fs RMS
- Random period jitter <30fs RMS
- LL effective loop bandwidth can be arbitrarily small
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1.013 to 1.217 GHz phase-locked loop
- AMS SiGe BiCMOS 0.35um
- Reference frequency from 10MHz to 125MHz
- LO1 frequency range from 1.013GHz to 1.127GHz
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Fractional-N PLL for Performance Computing in TSMC N6/N7
- Frequencies up to 4GHz
- Low jitter (< 10ps RMS)
- Small size (< 0.01 sq mm)
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Fractional-N PLL for Performance Computing in Samsung 8LPP
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.003 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
