General Purpose PLL IP

Compare 607 General Purpose PLL IP from 37 vendors (1 - 10)

4-Phase LC PLL on INTEL 16
- High performance design for meeting low jitter requirements including Ref Clock applications
- Implemented with Analog Bits’ proprietary LC architecture
- Low power consumption
- Integrated power supply regulation for low deterministic jitter
All Digital Phase Locked Loop
- The iniADPLL is an all digital implementation of a phase locked loop. Plls are widely used in telecom applications for clock recovery, clock generation and clock supervision.
- Different phase dtectors (FIFO fill level, phase erros, and so on) may be used and can be adapted to perfectely fit the application.
Multi-rate Audio DAC/PLL Core
- Operates from single 27/54MHz clock.
- Ideal for MPEG, AC-3, DVD systems
- Internally generates audio sample clocks
- Multi-sample rates: 32, 44.1, 48 KHz
Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
- Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
- Entirely core voltage powered, needs no analog supply voltage
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Very fine precision: near 1 part per billion resolution
Low Power 300-600 MHz programmable PLL
- The WEAPLL400M22 is a low power integer PLL operating at a single 0.8 V power supply
- This PLL has a wide programmable frequency range operation operating from 300 MHz up to 600 MHz
- The VCO outputs are coming into 8 cascaded phases
- The PLL needs a sourcing current of 2 uA in order to operate
General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- Output frequency range: 500MHz – 2GHz
- Loop bandwidth 60kHz – 180MHz
- 8 or 4 phase output clocks
- Output clock duty cycle 50 +5%
- Typically locks within 150 reference clock cycles
- Simple power-up sequence
- Lock indicator signal
Low Power PLL for TSMC 40nm ULP
- Wide range M, P, and N integer dividers.
- 40MHz – 600MHz output frequency range.
- Input frequency range 1.4MHz – 32MHz.
- 18pS RMS cycle to cycle jitter.
- Lock-detect function.
- Optional bypass function.
General Purpose PLL for TSMC 152nm
- Wide range M integer divider. (See ot3122 for M, N, and P dividers)
- 40MHz – 800MHz output frequency range.
- Comparable frequency range 8MHz – 32MHz.
- Optional prescaler.
- 19pS RMS cycle to cycle jitter at 800MHz.
- Lock-detect function.
- Bypass function.
- 20µS well defined fast startup behavior.
600MHz General Purpose PLL
- Wide range M integer divider. (See ot3122 for M, N, and P dividers)
- 250MHz – 600MHz output frequency range.
- Comparable frequency range 8MHz – 50MHz.
- 18pS RMS cycle to cycle jitter at 600MHz.
- Lock-detect function.
- Bypass function.
- Well defined startup behavior.
- -40°C to 140°C temperature operation.
1.2GHz General Purpose PLL for TSMC 0.18u Processes
- Wide range N, M integer dividers.
- 600MHz – 1.2GHz output frequency range.
- Comparable frequency range 20MHz – 200MHz.
- 18pS RMS cycle to cycle jitter at 1.2GHz.
- Lock-detect function.
- Bypass function.
- Well defined startup behavior.
- -40°C to 140°C temperature operation.