General Purpose PLL IP

Compare 607 General Purpose PLL IP from 38 vendors (1 - 10)

50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- 055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz.
- It consists of the ring VCO with frequency from 400 to 800MHz, a programmable feedback divider, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with internal loop filter, lock detector (LD) and programmable clock divider to obtain a required output frequency.
- LO output signal is CMOS compatible.
ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
- Clock generation based on a Digitally Controlled Oscillator (DCO)
- 800 MHz < = DCO frequency < = 2400 MHz
- Programmable clock frequency dividers for ADPLL loop and clock outputs
- lock-in < 25 us
All Digital Fractional-N PLL for Performance Computing in UMC 40LP
- Fractional multiplication with frequency up to 4GHz
- Low jitter (< 10ps RMS)
- Small size (< 0.01 sq mm)
- Low Power (< 5mW)
Integer PLL on Samsung 8nm LN08LPP
- PLLF0816X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
- It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, and an automatic frequency control (AFC).
Multi-rate Audio 24-Bit DAC/PLL Core
- Operates from single 27/54MHz clock.
- Ideal for MPEG, AC-3, DVD systems
- Internally generates audio sample clocks
- Multi-sample rates: 32, 44.1, 48 KHz
High Speed 16GHz PLL
- Type II ,3rd order low jitter PLL
- Auto calibration for process and temperature (USP)
- Programmable frequency using CSR registers
- 8/10/16GHz quadrature clocks
- Operating temperature -40 to 125
4-Phase LC PLL on INTEL 16
- High performance design for meeting low jitter requirements including Ref Clock applications
- Implemented with Analog Bits’ proprietary LC architecture
- Low power consumption
- Integrated power supply regulation for low deterministic jitter
All Digital Phase Locked Loop
- The iniADPLL is an all digital implementation of a phase locked loop. Plls are widely used in telecom applications for clock recovery, clock generation and clock supervision.
- Different phase dtectors (FIFO fill level, phase erros, and so on) may be used and can be adapted to perfectely fit the application.
Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
- Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
- Entirely core voltage powered, needs no analog supply voltage
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Very fine precision: near 1 part per billion resolution
Low Power 300-600 MHz programmable PLL
- The WEAPLL400M22 is a low power integer PLL operating at a single 0.8 V power supply
- This PLL has a wide programmable frequency range operation operating from 300 MHz up to 600 MHz
- The VCO outputs are coming into 8 cascaded phases
- The PLL needs a sourcing current of 2 uA in order to operate