Getting your Zynq SoC design up and running using PlanAhead
Adam Taylor, EADS Astrium
EETimes (2/8/2013 11:22 AM EST)
The Zynq-7000 All Programmable SoC is the first of a new class of Xilinx devices that marry a dual-core ARM Cortex-A9 processor with programmable logic on a single chip. As such, the device offers a great leap forward in not only system flexibility, but also performance and integration. This system-on-chip platform does, however, require the FPGA engineer to consider a slightly different development path than is customary for logic-based FPGAs.
The good news is that development is not as difficult as you might think, thanks in large part to the availability of the Xilinx PlanAhead tool. Let’s take a closer look at the steps involved in generating a Zynq-7000 system that you can load via JTAG.
To read the full article, click here
Related Semiconductor IP
- ARC4 Core for Xilinx FPG
- Xilinx Virtual Cable
- Xilinx HMC Controller
- Xilinx MicroBlaze Trace Core (XMTC)
- Xilinx Kintex 7 NVME HOST IP
Related White Papers
- Agile Verification for SoC Design
- EDA in the Cloud Will be Key to Rapid Innovative SoC Design
- Low Power Design in SoC Using Arm IP
- Multi Voltage SoC Power Design Technique
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design