Desperately Seeking Solutions to the verification nightmare
Lauro Rizzatti, EVE USA
EETimes (9/21/2010 12:19 PM EDT)
SoC design teams are desperate to find solutions to the verification nightmare. Solutions come in abundance, but not all are what they claim. A situation so outrageous it takes a new and versatile approach to solve it; for example, high-performance FPGA prototyping platforms.These days, the C in SoC could stand for "complexity" and not "chip" due to the explosion of embedded software just as design teams juggle hundreds of millions – or even billions – of gates. Several design teams currently budgeting for their next project have calculated that the software portion of a system on chip (SoC) is on an annual growth rate of 140 percent. Hardware is expanding at approximately 40 percent year to year. All this goes on as the time-to-market budget condenses and verification nightmares grow.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
- Neural Video Processor IP
Related White Papers
- Network processor designer tackles verification 'nightmare'
- How to transform video SerDes from a nightmare to a dream
- Verification care abouts for SoC internal channel characterization using an ADC
- Verification challenges of ADC subsystem integration within an SoC
Latest White Papers
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
- CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions