Desperately Seeking Solutions to the verification nightmare
Lauro Rizzatti, EVE USA
EETimes (9/21/2010 12:19 PM EDT)
SoC design teams are desperate to find solutions to the verification nightmare. Solutions come in abundance, but not all are what they claim. A situation so outrageous it takes a new and versatile approach to solve it; for example, high-performance FPGA prototyping platforms.These days, the C in SoC could stand for "complexity" and not "chip" due to the explosion of embedded software just as design teams juggle hundreds of millions – or even billions – of gates. Several design teams currently budgeting for their next project have calculated that the software portion of a system on chip (SoC) is on an annual growth rate of 140 percent. Hardware is expanding at approximately 40 percent year to year. All this goes on as the time-to-market budget condenses and verification nightmares grow.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- Network processor designer tackles verification 'nightmare'
- How to transform video SerDes from a nightmare to a dream
- Reusable Test-Case Methodology for SoC Verification
- Plug-n-play UVM Environment for Verification of Interrupts in an IP
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS